WLAN Transceiver Research Articles

A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

ELC metamaterial based CPW‐fed printed dual‐band antenna

ABSTRACTThis letter presents metamaterial (MTM) based dual band antenna. Two resonances are obtained by making use of square ELC (Electric‐inductive‐capacitive) resonator and CR (Closed Ring) resonator. This research evolves an antenna having dimension only of 21 × 30 × 1.6 mm3 which operates at two bands from 3.28 GHz to 4.52 GHz and from 5.20 GHz to 5.87 GHz. This antenna can be useful for WiMAX and WLAN transceiver at 3.5 GHz and 5 GHz band respectively. It can also be used in RFID applications at 3.9 GHz band. This paper includes the parametric investigations as well as measurement details. Simulation and measurement data have shown good equivalence which emphasis the practicability of the proposed antenna. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:304–307, 2017

Sequential specification of time-aware stream processing applications

Automatic parallelization of Nested Loop Programs (NLPs) is an attractive method to create embedded real-time stream processing applications for multi-core systems. However, the description and parallelization of applications with a time dependent functional behavior has not been considered in NLPs. In such a description, semantic information about time dependent behavior must be made available for the compiler, such that an optimized time independent implementation can be generated automatically. This article introduces language constructs with temporal semantics to NLPs. Using these language constructs, time dependent applications can be specified and a corresponding data-driven implementation can be generated for use on a multi-core system. Despite that these time-aware language constructs can be data-dependent, the application remains functionally deterministic. Pipelining is exploited to increase the throughput of an application. The media access control (MAC) protocol of an IEEE 802.11p WLAN transceiver is used to illustrate the relevance and applicability of the introduced concepts.

MAC and baseband processors for RF-MIMO WLAN

The article describes hardware solutions for the IEEE 802.11 medium access control (MAC) layer and IEEE 802.11a digital baseband in an RF-MIMO WLAN transceiver that performs the signal combining in the analogue domain. Architecture and implementation details of the MAC processor including a hardware accelerator and a 16-bit MAC-physical layer (PHY) interface are presented. The proposed hardware solution is tested and verified using a PHY link emulator. Architecture, design, implementation, and test of a reconfigurable digital baseband processor are described too. Description includes the baseband algorithms (the main blocks being MIMO channel estimation and Tx-Rx analogue beamforming), their FPGA-based implementation, baseband printed-circuit-board, and real-time tests.

Analytic Study of Synchronization Errors in OFDM System Applied on WLAN Transceiver

Analytic Study of Synchronization Errors in OFDM System Applied on WLAN Transceiver

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

A high-linearity PGA (programmable gain amplifier) with a DC offset calibration loop is proposed. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated by TSMC 0.13 μm CMOS technology. The measurements show that the receiver PGA (RXPGA) provides a 64 dB gain range with a step of 1 dB, and the transmitter PGA (TXPGA) covers a 16 dB gain. The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply. The bandwidth of the multi-stage PGA is higher than 20 MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10 kHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45 μs.

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration (5.88 mA after calibration) from 2.85 V supply. Implemented in a 0.35 μm SiGe technology, they occupy 0.68 mm2 and 0.18 mm2 die size respectively.

LC‐active VCO for CMOS RF transceivers

AbstractA novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability.In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of −129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.

Embedded ranging system in ISM band

A new embedded ranging system in the ISM band is described. The proposed indoor ranging system combines the advantages of both broadband and narrowband signals to achieve high ranging accuracy in the presence of strong multipath reflections to achieve a good link budget and to be compliant with spectral regulations. The system is based on a WLAN transceiver (with embedded ranging specific circuits) and uses the same frequency band for both communication and ranging purposes so that no separate dedicated ranging transceiver is needed. A prototype has been implemented to evaluate the performance of the proposed technique in a realistic environment. Experimental results show ranging accuracies of less than 20 cm.

Digital Automatic Gain Control Integrated on WLAN Platform

� Abstract—In this work we present a solution for DAGC (Digital Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4 GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used enables gain control over Low Noise Amplifier (LNA) and a Variable Gain Amplifier (VGA). The control over those signals is performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the average power of the baseband signal close to the desired set point. DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal, accumulating the differences between the measured power level and actual gain setting, adjusting a gain factor of the accumulation, and applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us. Keywords—WLAN, AGC, RSSI, baseband processor.

OFDM Synchronization Errors and Effects of Phase Noise on WLAN Transceivers

This work aims at frequency synchronization in OFDM IEEE 802.11g Transceivers. The degradation of performance results from the detrimental effects introduced by frequency offset and phase noise. First, we present a robust method to detect and synchronize the OFDM signal with severe noise and interference corruption based on calculating the accumulated phase difference for each subcarrier. Then, we present a simple architecture to implement the proposed methods. These methods are simulated and analyzed by computer. Finally, we propose many algorithms to correct the common phase error (CPE) of the phase noise and track well its variation.

A 3.5‐GHz, low voltage, current draining folded mixer in 0.18‐μm CMOS technology

PurposeThis paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.Design/methodology/approachA folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P−1dB), power dissipation and reduction of switching quad Cgs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.FindingsA highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P−1dB in 0.18‐μm CMOS technology.Research limitations/implicationsThe optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.Practical implicationsThe designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.Originality/valueIn this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA

A low-power fullband 802.11a/b/g WLAN transceiver in 0.15-mum CMOS technology is described. The zero-IF transceiver achieves a receiver noise figure of 4.4/4 dB for the 2.4-GHz/5-GHz bands, respectively. The corresponding sensitivity at 54-Mb/s operation is -72 dBm for 802.11g and -74 dBm for 802.11a using actual PER measurement. An on-chip PA delivers 20 dBm output P1-dB. A new I/Q compensation scheme is implemented in local oscillator (LO) and an image rejection of better than 52 dB is observed. The transmitter delivers 10/1.5 dBm (2.4-/5-GHz) EVM-compliant output power for a 64-QAM OFDM signal at 54-Mb/s. The power consumption is 117/135 mW (1.8-V) in the receive mode and 570/233.1 mW in the transmit mode for 2.4/5 GHz, respectively. The low power consumption, high integration and robustness (-40 to 140degC) make this transceiver suitable for portable applications

CMOS dual-band variable-gain amplifier for 3G-WCDMA and WLAN dual-mode RF receivers

A dual-band variable-gain amplifier (DBVGA) is presented for integrated 2.2 GHz 3G-WCDMA and 5.2 GHz WLAN transceivers. DBVGA employs a DC-and-RF current steering technique for gain control, which can minimise variations of the noise, 1 dB gain compression point, and input/output impedance when the gain is tuned. The appropriate frequency operation band of DBVGA is jointly controlled by the switched-resonator load and the input stage gate bias, resulting in high cross-band isolation and out-of-band interference rejection. All circuits except the input stages are reused for both bands to have high component reuse. A fully-integrated 0.18 µm CMOS DBVGA has been implemented to verify the proposed design.

A 5-GHz 108-Mb/s 2$\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS

Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2times2 MIMO WLAN transceiver RFIC implemented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO performance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of -63 dBm while receiving 108Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of AWGN noise is -76 dBm. Linearized 3.3-V 5-GHz power amplifiers with P1dB=20.5 dBm deliver an average power of +13/+16 dBm each, in MIMO/SISO modes respectively (EVM=-27/-25 dB). The measured performance demonstrates the effectiveness of the isolation techniques employed. The system in a package includes an 18 mm2 die and microstrip front-end matching networks implemented on a flip-chip package

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), ?18 dBm input 1 dB compression point (ICP) and ?7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard.

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and ...

An integrated cmos rf synthesizer for 802.11a wireless lan

A frequency synthesizer combining a relatively large tuning range (4.12-4.72 GHz) with a low noise sensitivity is presented. A stable fine-tuning loop is combined with an unstable coarse-tuning loop in parallel. As a result, a stable phase-locked loop (PLL) with a relatively wide tuning range and a moderate level of reference spurs is obtained. By adding a resistorless coarse-tuning loop, the tuning range was increased by a factor of four with no penalty in terms of phase noise, reference spurs, and settling speed. Also, the additional chip area and power consumption are negligible. The CMOS PLL circuit fabricated in a 0.25-μm technology is aimed at multiband WLAN transceivers.