Wireline Communication Research Articles

A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology

—A 64Gbps 4-level pulse amplitude modulation (PAM4) mixed-signal receiver incorporating a decision-feedback equalizer (DFE) for application in wireline communication is implemented in fully-depleted silicon-on-insulator (FDSOI) 22nm technology. A two-stage slicer with body biasing is proposed to alleviate the stringent timing constraint of the closed-loop DFE. The smaller loading of the first stage shortens the output delay so as to provide a much larger differential input for the second stage. Moreover, body biasing is applied to the proposed slicer to allow higher drive and faster switching capabilities. Simulation results demonstrate that the receiver with body biased two-stage slicer achieves at least 9.9 % and 14.3 % improvements in recovered eye height and eye width over the receiver with StrongArm slicer. The receiver consumes a power of 117.1mW, achieving 1.83pJ/bit energy efficiency.

Multi-Channel Nonlinearity Mitigation Using Machine Learning Algorithms

This paper investigates multi-channel machine learning (ML) techniques in the presence of receiver nonlinearities and noise, and compares the results with the single-channel receiver architecture. It is known that the multi-channel architecture relaxes the sampling speed requirement of analog to digital conversion and provides significant robustness to clock jitter and front-end noise due to the bandwidth-splitting property inherent in these receivers. However, when a high-voltage swing signal is used in a wireline communication link, the received signal suffers from third-order harmonic distortions and inter-modulation products caused by the nonlinearity profile of the analog front-end (AFE). To this end, this paper proposes the channel decision passing (CDP) algorithm in combination with nonlinear feedback cancellation as a low-complexity candidate for nonlinearity mitigation and compares the performance of this solution with other well-known ML algorithms. Simulation results show significant improvement in a multi-channel receiver architecture equipped with nonlinear feedback cancellation and CDP in comparison with its single-channel counterpart under practical nonlinearity profiles and noise conditions.

Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication

Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication

FBMC vs. PAM and DMT for High-Speed Wireline Communication

FBMC vs. PAM and DMT for High-Speed Wireline Communication

Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication

Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication

An Electromagnetic Interference Immune PAM-4 Transceiver System

This article presents the design of a pulse amplitude modulation (PAM-4) transceiver that supports high-speed wireline communication in the presence of electromagnetic interference (EMI). The proposed PAM-4 transceiver uses an input level shifter (ILS) and a modified electrostatic discharge (ESD)-protection circuit to reduce the effects of EMI at the transmitter. In order to overcome the effects of EMI at the receiver, the front end is designed with an enhanced input common-mode range. The transverse electromagnetic (TEM) cell method, as provided in the IEC 62132-2 standard, is followed to experimentally verify the radiated EMI-immunity of the proposed PAM-4 transceiver system over its traditional counterpart. For proof of concept, the proposed EMI-immune PAM-4 transceiver and the traditional PAM-4 transceiver circuits are implemented using the 130-nm BiCMOS process. The proposed transceiver operates at a data rate of 6.5 Gbps while maintaining an eye-opening of 70 mV for each bit in the presence of EMI, meeting the requirement of the IEEE 802.3 bs standard. The proposed PAM-4 transceiver withstands a wide range of EMI frequencies that span from 150 kHz to 2 GHz with an EMI power of 0–20 dBm.

Evaluation Fiber Optic Communication Network Performance through Manchester Code

There has been, and will continue to be, discussion over how to monitor wireline communications with increased data rates. In order to meet bandwidth requirements while keeping complexity at an acceptable level, engineers have dealt with many data formats over the years. Manchester encoding is a popular choice among the current solutions for various applications. Another benefit in high-speed input-output lines when the power budget is limited is the Manchester coding transceiver, which can be realized in a reasonably simple fashion. For inexpensive digital data optical transmission, the Manchester data format can be utilised as a modulation mechanism. The performance of the related transceivers under different conditions can be estimated by doing a comprehensive analysis of the Manchester data format and comparing it with other line coding types. System developed and fine-tuned for performance and feasibility evaluation. We used Opti system 2014 to test the system.

A PVT tolerant latch in a 90-nm CMOS and performances under AC noise

ABSTRACT Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

Transition‐limited pulse‐amplitude modulation technique for high‐speed wireline communication systems

AbstractThis paper presents a transition‐limited pulse‐amplitude modulation (TLPAM) signaling method to enable a high data rate and robust wireline communications. TLPAM signaling addresses the impact of high intersymbol interference (ISI) ratios in conventional M‐ary PAM signaling methods by limiting the maximum voltage transition level between adjacent symbols. The implementation of a TLPAM signaling encoder is realized by setting back the most significant bits (MSBs) in the queue. The correlation between TLPAM's maximum transition level, effective data rate, and eye width/height is analyzed with various channel loss parameters, followed by characterization and measurement results with a realistic channel setup. The analysis and experimental results reveal the effectiveness of the proposed TLPAM signaling scheme for achieving a high data rate with minimal interference.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme

The required data rate of wireline communications has increased; however, channel attenuation limits the data bandwidth. Bit-efficient signaling is an effective and efficient solution because more data can be transmitted at the same Nyquist frequency. Several methods for increasing bit efficiency, such as multi-wire signaling, multi-level signaling, and symbol correlation schemes, have been proposed. Each scheme can generate additional codes by encoding the data. Additional codes can be used to transmit more data or to embed data transitions. In this study, the aforementioned schemes are analyzed, and a method is developed to combine them, maximize the bit efficiency, and ensure the data transition density. For the prototype transceiver, a 4-wire PAM-3 (4W3P) signaling scheme was adopted. The 4W3P signaling scheme can increase the bit efficiency to 200% while maintaining the DC-balanced characteristics. Transceiver building blocks, such as the TX driver, feed-forward equalizer, and analog front-end, were optimized for the proposed signaling scheme. The prototype transceiver was fabricated using 28 nm CMOS technology, occupying 0.012 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The RX was measured using the TX and achieved a BER less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-12}$ </tex-math></inline-formula> at 40 Gb/s over the four wires, with a total transceiver energy efficiency of 1.52 pJ/bit.

A High-Density and Low-Crosstalk Differential Pin Map for 112 Gb/s PAM4 Applications

The rapidly growing demand for high-bandwidth data rate has pushed the wireline communications speed up to 112 Gb/s. In such high-speed and high-channel-count applications, a major challenge for differential pin map design is the tradeoff between cost and the crosstalk between differential pairs in the area of BGA pins and PCB via connection. In this letter, a pin map pattern with a high signal-to-ground ratio (S:G) of 1:1.25 and low crosstalk is proposed. Compared with the conventional pin map pattern in a square array with S:G &#x003D; 1:1, the integrated crosstalk noise (ICN) is reduced by 75&#x0025; and the insertion loss to crosstalk ratio (ICR) is increased by 13 dB. Compared with the conventional pin map pattern in a triangular array with S:G &#x003D; 1:1.5, the ICN is reduced by 20&#x0025;, and the ICR is improved by 3 dB.

Bridging the Terahertz Gap: Photonics-Assisted Free-Space Communications From the Submillimeter-Wave to the Mid-Infrared

Since about one and half centuries ago, at the dawn of modern communications, the radio and the optics have been two separate electromagnetic spectrum regions to carry data. Differentiated by their generation&#x002F;detection methods and propagation properties, the two paths have evolved almost independently until today. The optical technologies dominate the long-distance and high-speed terrestrial wireline communications through fiber-optic telecom systems, whereas the radio technologies have mainly dominated the short- to medium-range wireless scenarios. Now, these two separate counterparts are both facing a sign of saturation in their respective roadmap horizons, particularly in the segment of free-space communications. The optical technologies are extending into the mid-wave and long-wave infrared (MWIR and LWIR) regimes to achieve better propagation performance through the dynamic atmospheric channels. Radio technologies strive for higher frequencies like the millimeter-wave (MMW) and sub-terahertz (sub-THz) to gain broader bandwidth. The boundary between the two is becoming blurred and intercrossed. During the past few years, we witnessed technological breakthroughs in free-space transmission supporting very high data rates, many achieved with the assistance of photonics. This paper focuses on such photonics-assisted free-space communication technologies in both the lower and upper sides of the THz gap and provides a detailed review of recent research and development activities on some of the key enabling technologies. Our recent experimental demonstrations of high-speed free-space transmissions in both frequency regions are also presented as examples to show the system requirements for device characteristics and digital signal processing (DSP) performance.

Recurrent Neural Network Equalization for Wireline Communication Systems

Satisfying the demand for ever increasing data rates in wireline communication systems is challenging due to high frequency-dependent channel insertion loss causing significant inter-symbol interference (ISI). This motivates the use of ADC-based receiver architectures that allow for digital equalizer implementations. However, the large tap count feed-forward equalizers (FFEs) required at high data rates causes noise enhancement that can degrade signal-to-noise ratio (SNR) and high complexity is required to implement multi-tap decision feedback equalizers (DFEs). Moreover, analog front-end (AFE) nonlinearity can limit the performance of these traditional FFE-DFE architectures. This brief investigates an alternative approach with recurrent neural network (RNN) equalization based on long short-term memory (LSTM) and gate recurrent unit (GRU) cells. 64 Gb/s PAM4 modeling results show that the RNN topologies offer significant BER improvement over a wide SNR range for a channel with 30 dB loss at 16 GHz and enable operation over a channel with a large notch at 10 GHz that the traditional FFE-DFE topology cannot support. Synthesis results utilizing a 22 nm FinFET process yield only a 34% and 29% increase in receiver power consumption for the LSTM and GRU implementations, respectively, to enable this improved performance.

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36&#x0025;, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate <inline-formula> <tex-math notation="LaTeX">$&lt; 1\text{E}$ </tex-math></inline-formula>-10 with a power efficiency of 4.75 pJ/bit.

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters&#x2019; resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor&#x2019;s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

FUZZY-LOGICAL EXPERT SYSTEM FOR ASSESSING THE FINANCIAL SECURITY OF ENTERPRISES

The purpose of this study is to build a fuzzy expert system for assessing the financial component of the economic security of telecommunications enterprises. The methodological basis of the research is founded on scientific works of domestic and foreign scientists and leading experts in the field of financial analysis and modeling of economic processes, as well as statistical and financial reporting data that are publicly available. To construct an integral indicator of the financial security of an enterprise, a fuzzy conclusion is used. Three financial indicators are used as input variables. The first indicator X1 is the Current Ratio (CR). The second indicator X2 is Equity Ratio (ER). The third indicator is Return on Assets (ROA). The output variable is defined as an indicator of the financial security of an enterprise Y123 (FS). Both the input variables and the output variable are converted to fuzziness by constructing membership functions. The type and parameters of the affiliation function are justified, and the bell-shaped affiliation function is chosen to describe the uncertainty of values that fall under the normal distribution. The quantity of fuzzy sets at every input is considered as z=3 and the quantity of input variables is considered as ω=3. To achieve completeness of the model, the quantity of logic rules is considered as r=33=9. To calculate a degree of market concentration, Mamdani fuzzy conclusion is applied. Defuzzification is engaged to calculate the value of the output variable Y123(FS) for an indicator that determines the degree of financial security of an enterprise and, as a result, the degree of its economic security. To assess the level of the financial security indicator of an enterprise, a fuzzy expert system is constructed. The fuzzy expert system allows you to use various indicators thanks to the fuzzy logic methodology, which takes into account the fuzziness of input variables and output variables as much as possible. For the three telecommunications companies whose core business is wireline communication, ratios are calculated based on financial reports. Financial coefficients are used to determine the integral indicator of financial security of enterprises. This indicator can be characterized by both numerical values and linguistic terms.

A Methodology to Emulate the Effect of EMI in Circuit Simulators for Wireline Communication Channel

This letter presents a methodology to model the effect of electromagnetic interference (EMI) on the wireline communication channels. The proposed simulation methodology incorporates the effect of EMI on the circuit during the design phase in EMI-sensitive applications. It allows simple and faster EMI simulations at the SPICE level which minimizes the post-fabrication failures. A TEM (transverse electromagnetic) cell is used to emulate the effect of EMI on the test circuit as provided in the standard IEC-62132. An analytical model is presented to quantify the effect of induced voltage and current on a transmission line placed in the TEM cell. The developed model is experimentally verified for a frequency range of 1 MHz to 1 GHz. As an experimental study, the proposed model is used to validate the effect of EMI on the wireline communication channel transmitting a pseudorandom binary sequence (PRBS) data generated from an FPGA board at 1 Gbps data rate for a wide range of EMI powers and frequencies.

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

AbstractThis paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.