Driven by the smaller, faster and cheaper demands of advanced microelectronic devices, the modern packages are required to increase I/O numbers, reduce die and package sizes and lower manufacturing costs. Although, today’s microelectronic devices have many modern types of package, e.g. flip chip, wafer level packaging and tape automated bonding technologies, wire bonding is still the dominant microelectronic packaging technology.To provide more functions within a package, the 3-dimensional and multi-chip modules have come to be the solution of choice in delivering higher integration, smaller and more functional products for meeting consumer requirements, especially in the portable and handheld electrical products.Since the interconnection distance of the multi-chip modules is usually longer than that of a single-chip system, concerns about wire sweep and wire sag for the applications of 3-dimensional packaging technology in the multi-chip module systems have been highly mentioned recently.This has been ascertained by the author in previous studies, the longer the bond length and the higher the bond height of a wire bond, the smaller the sweep stiffness of the bond system becomes. The lower sweep stiffness of the wire bond will always cause higher risk of wire sweep. Consequently, for 3-dimensional and multi-chip packaging, excessive wire sag can lead to wire touch in the lower layer and thereby causing short circuits and malfunction of chips.Wire sag problems are very crucial to the applications of 3-dimensional and multi-chip packaging in semiconductor industry. To authors’ knowledge, this issue has never been investigated. The main purpose of this paper will be to study in depth the wire sag problem for long wire bonds, applied in 3-dimensional and/or in multi-chip module packaging. A definition of the sag stiffness of a wire bond will be shown to represent sag resistance of specific profiles of wire bond. The author will also present wire sag experiments of wire bonds thereby verifying numerical analysis.
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