Wide Range Of Supply Voltages Research Articles

Fixed-Frequency Boundary Control of Buck Converter With Second-Order Switching Surface

This paper presents a fixed-frequency boundary control of buck converters. The method is based on integrating the concept of variable hysteresis into the boundary control technique with second-order switching surface. The switching frequency is maintained constant over a wide range of supply voltages and output loads. The method is based on using a frequency-to-voltage converter and comparing its output voltage with a reference voltage to control the width of the hysteresis in the boundary controller. It also combines the advantages of the boundary control that the converter can reach the steady state in two switching actions after large-signal disturbances. The basic operating principles, stability analysis, and design procedures will be given. The proposed control method has been successfully applied to control a 140 W, 24 V/12 V buck converter. The steady-state characteristics, including the switching frequency and output voltage ripple, at different input voltages and output loads with and without the proposed control method have been compared. The system responses under large-signal supply voltage and load disturbances will be discussed.

Wide $V_{\rm DD}$ Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems

Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous static random-access memory (SRAM). Data-dependent bitline-leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage, and temperature conditions. The DMST technique employs a single replica column and new dummy cells to track both precharge and sensing activities in asynchronous SRAM, with bitline leakage considered. The DMST-technique simulation uses both 65-nm and 0.35-mum technologies. Several 0.35-mum DMST SRAM macros were fabricated in a test chip and embedded in a mass-produced system-on-a-chip suitable for various battery/supply-voltage configurations. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3 V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths and offers the same area overhead as conventional sense-tracking-only replica-column schemes.

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18µm CMOS technology, and the simulation results show 86dB of dynamic range with 4.5µVrms of input-referred noise for an audio bandwidth of 20kHz and a total harmonic distortion (THD) of 1% at 90mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95dB at 1kHz. The proposed design dissipates 125µA and can operate over a wide supply voltage range of 1.6V to 3.3V.

DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE

In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

A Programmable 0.8-V 10-bit 60-MS/s 19.2-mW 0.13-$\mu$m CMOS ADC Operating Down to 0.5 V

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This work describes a programmable 10- to 100-MS/s, low-power 10-bit two-step pipeline analog–digital converter (ADC) operating at a power supply from 0.5- to 1.2-V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5-V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10-bit accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the multiplying digital-to-analog converter, while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13-<formula> <tex>$\mu$</tex></formula>m CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 0.35 and 0.49 least significant bits. The ADC, with an active die area of 0.98 mm<formula formulatype="inline"> <tex>$^{2}$</tex></formula>, shows a maximum signal-to-noise distortion ratio and spurious free dynamic range of 56.0 and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s. </para>

A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.

The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style

This paper introduces a high-throughput asynchronous pipeline style, called high-capacity (HC) pipelines, targeted to datapaths that use dynamic logic. This approach includes a novel highly-concurrent handshake protocol, with fewer synchronization points between neighboring pipeline stages than almost all existing asynchronous dynamic pipelining approaches. Furthermore, the dynamic pipelines provide 100% buffering capacity, without explicit latches, by means of separate pullup and pulldown control for each pipeline stage: neighboring stages can store distinct data items, unlike almost all existing latchless dynamic asynchronous pipelines. As a result, very high throughput is obtained. Fabricated first-input-first-output (FIFO) designs, in 0.18-m technology, were fully functional over a wide range of supply voltages (1.2 to over 2.5 V), exhibiting a corresponding range of throughputs from 1.0-2.4 giga items/s. In addition, an experimental finite-impulse response (FIR) filter chip was designed and fabricated with IBM Research, whose speed-critical core used an HC pipeline. The HC pipeline exhibited throughputs up to 1.8 giga items/s, and the overall filter achieved 1.32 giga items/s, thus obtaining 15% higher throughput and 50% lower latency than the fastest previously-reported synchronous FIR filter, also designed at IBM Research.

Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in the header/footer device and provides a wide range of virtual ground (GND) or supply voltage. Physical analysis and numerical mix-mode device/circuit-simulation results confirm that the proposed scheme can be applied to low-power high-performance circuit applications in 65-nm technology node and beyond. Variable/dynamic supply or GND voltage using the proposed scheme improves read and write margins in scaled SRAM without degrading read and write performance.

Investigations of amplitude and time characteristics of ФЭУ-187 photomultiplier tubes with fine-mesh dynodes

Investigation results of new models of the ФЭУ-187 photomultiplier tube with fine-mesh dynodes are described. The gain and time characteristics are measured by using a laser pulsed source both with no magnetic field and in magnetic fields of up to 0.5 T. It is shown that, in magnetic fields of up to 0.5 T, the time resolution of the photomultiplier tube does not deteriorate in a wide supply-voltage range. The basic demand of the ALICE (Large Ion Collider Experiment) experiment (Large Hadron Collider, CERN, Switzerland)—that the time resolution was at least 35 ps during detection of about 180 photoelectrons—is met for all the tested models.

Design of an Optimized 2.5 GHz CMOS Differential LC Oscillator with Nonlinear Analysis for MOS Varactor

The oscillation amplitude and supply current relations for a differential CMOS oscillator are derived by using an analytic method. A simplified model to predict the phase noise performance of the oscillator is developed. The large signal analysis of a nonlinear inversion mode MOS varactor is presented. The derived expressions can help to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the method has been verified by designing an LC CMOS oscillator in a 0.25 ?m CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.

Design of an optimised 2.5 GHz CMOS differential LC oscillator

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS oscillator. A simplified model to predict the phase noise performance for this type of oscillator is developed. Using this method, it becomes possible to design an optimised oscillator in terms of a minimum phase noise and low power consumption. The validity of the method has been verified by designing a LC CMOS oscillator using 0.25 /spl mu/m CMOS technology. The predictions are in good agreement with simulation results over a wide range of the supply voltage.

Optimised analytic designed 2.5 GHz CMOS VCO

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 µm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage.

Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 μm CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 μA of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.

Design techniques for EEPROMs embedded in portable systems on chips

These design techniques target EEPROMs embedded in portable, battery-powered devices that operate under a wide supply voltage range. A current-controlled ring oscillator provides stable programming pulse generation, optimizing write time. Logic delay optimization and a word line boosting technique decrease read access time.

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

This paper describes a 128-kb FeRAM macro for smart-card microcontrollers. This macro, which was designed and fabricated using a 0.35-/spl mu/m three-metal CMOS and a Capacitor-on-Metal/Via-stacked-Plug (CMVP) process technology, is ideally suited for recent system LSIs such as smart-card microcontrollers. It has a flexible memory size ranging from 32 to 128 kb, a low consumption current of 0.3 mA, and endurance of more than 10/sup 8/ write/read cycles under a wide range of supply voltages, from 2.7 to 5.5 V. These characteristics, which are required of not only contact-type smart-card microcontrollers but also contactless-type ones, were achieved by using four newly developed circuit technologies: 1) a three-metal CMVP memory cell; 2) a voltage-regulating architecture; 3) a main/sub bitline and wordline structure; and 4) a dynamic-type offset sense amplifier.

Low-voltage low-power accurate CMOS V/sub T/ extractor

Circuits extracting a MOSFET's threshold voltage belong to the general category of bias circuits. Since these circuits do not process signal inputs, their power consumption should be low, while preserving high accuracy and robustness of the output against supply voltage variations and transistor mismatch. In this work, a low-voltage low-power self-biased analog CMOS V/sub T/ extractor is proposed. By utilizing novel feedback on a simple low-voltage V/sub T/ extracting block, the extractor presents less than 0.3% error for wide supply voltage range, and achieves low-power consumption and self-compensation for second-order effects and mismatch. These features are supported by simulation results.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Class AB output stage for low voltage CMOS op-ampswith accuratequiescent current control

A new class AB output stage for CMOS op-amps, with accurate quiescent and minimum current control, is proposed. The proposed stage can be operated with a supply voltage close to the threshold voltage of the transistor. A dynamic biasing scheme allows it to operate over a wide range of supply voltages. Simulation results are provided that are in good agreement with expected values.