Wide OR Gates Research Articles

New partitioned domino circuit for power-efficient wide gates

In this article, a new domino circuit is presented to decrease the power consumption of wide gates without considerable performance and robustness degradation. The suggested circuit technique modifies the output inverter to decrease the switching power by decreasing the voltage swing. Moreover, the wide pull-down networks can be partitioned into smaller networks. To merge the partitioned pull-down networks, a dynamic NAND gate is employed to increase the circuit performance. Using the proposed technique, the leakage current is decreased in the wide gates because of the stacking effect. Also, the noise immunity is improved due to the body effect. The wide OR gates are simulated in 90-nm CMOS technology. Simulation results show 54% power reduction and 2.55 times improvement in the noise immunity at the same speed in comparison with the conventional circuit technique for 64-input OR gates. In addition, a 128-input AND-OR gate is designed using the proposed circuit. Results demonstrate that power and delay are reduced by 39% and 11%, respectively, compared to the conventional AND-OR gate at the same robustness.

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. The main idea in the proposed circuit is using sense amplifier for sensing the difference between voltages across the pull down network (PDN). This strategy provides correct output. In the proposed technique, therefore, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-bit wide OR gates using a 90nm CMOS technology model. The simulation results are compared with that of standard domino circuits at the same delay, and 35% power consumption reduction and 2.31× noise-immunity improvement are observed.