Wafer Transfer Research Articles

Transfer and handling of thin semiconductor materials by a combination of wafer bonding and controlled crack propagation

ABSTRACTDirect waferbonding is an appropriate technology to join two or more wafers of the same or of different materials. Waferbonding can be used to stiffen thin wafers during fabrication. However, conventional fabrication processes lead to an increase of the bond strength, which inhibits the required de-bonding. The propagation of cracks, which is based on a subcritical crack growth in the bonded interface, was used to cleave the bonded wafers. The subcritical crack growth is limited to the bonded interface, since the adjacent bulk semiconductor materials are inherently resistant to subcritical crack growth. The process allows the separation of Si-Si and Si-GaAs wafers after annealing. Wafer-bonded SOI wafers can also be separated with this technology even if they were annealed at 1100°C. The first examples for wafer stiffening during fabrication and wafer transfer using the developed approach will be presented.

Calibration for wafer transfer robot

Calibration for wafer transfer robot

Mechanical lapping, handling and transfer of ultra-thin wafers

This paper presents a new technique for thinning down up to 10 m and handling various semiconductor devices, and transferring them onto host substrates. An optimized mechanical lapping is used to remove the wafer backside after the fabrication process by way of a cavity-wafer. The original transfer technique based on the different thermal properties of waxes or epoxy layers is described, and the electrical results obtained on test devices are presented.

Mixing and Matching Deep-UV Step-and-Scan with I-Line Step and Repeat

This paper reviews all the major aspects of successfully implementing a “mix and match” (Deep-UV/I-line, stepper/scanner) strategy. The resolution and linewidth-control limits of I-line are quantified for a number of the process levels and compared with the capabilities of Deep-UV step-and-scan. This analysis predicts the typical mix of steppers and scanners in a 256 MBit production line for 250 nm lithography. A step-by-step procedure to achieve and monitor successful matching is reviewed. The procedure begins by defining a “golden system”, which is used to produce reference wafers for the setup and monitoring of all the systems being mixed and matched. The reference wafers are used to ensure that the pre-aligners of the systems are calibrated and that offsets are adapted to allow the transfer of wafers between systems. The wafers are also used to match both wafer-stage grid and exposure-field distortions. The matching of both wafer-grid and stepper-field distortions are reviewed. The implementation of stage correction-tables is demonstrated. It is indicated that grid matching to better than 10 nm is achievable. It is also indicated that the dynamic scanning of a step-and-scan system allows the monitoring and correction of such typical stepper problems as field magnification and rotation. The critical aspects of multi-field matching between stepper and scanner are analyzed. The key factors that allow the successful overlaying of large, single, scanned fields with multiple, small, stepped fields are reviewed. The total overlay accuracy achieved using step-and-scan, and “mix-and-match” is analyzed and demonstrated.

Design and implementation of a precision material handling robot control system

Robotic transfer of silicon wafers in semiconductor fabrication facilities is becoming increasingly attractive. This paper discusses the benefits of a DSP-based computed torque controller over standard PID algorithms for a three degree of freedom, cleanroom material transfer manipulator. Formulation of robot kinematics, dynamic modeling, and numerical simulation assist in the implementation of this nonlinear controller. Simulation and experimental data correlate well and show that a factor of 2–3 times improvement in performance can be obtained.

Linear Drive Systems and their Related Technologies. Development of Magnetically Suspended Linear Pulse Motor for Contactless Direct Drive in Vacuum Chamber Robot.

In the semiconductor manufacturing industries, the demand for semiconductor wafer processes in an ultra-high vacuum chamber is increasing in connection with development of more highly integrated circuits. This may impose severer restrictions on wafer transfer robot with regard to contamination of the vacuum environment. In the severest case, a robot mechanism without use of lubricant, generation of dust particle and release of gases will be necessary. One of advantage methods for realizing such mechanism is to drive robot arm directly without mechanical contact by means of magnetic suspention techniques. For example, it is considered to employ a linear motor and magnetic bearings which are hermetically enclosed in a box-like casing.In this paper, a magnetically suspended linear pulse motor (LPM) is proposed as contactless direct drive mechanism of vacuum chamber robot. Here the major problem is a marked lowering of thrust caused by a broad air gap which must be arranged between stator teeth and mover ones in consideration of the wall thickness of the motor casing. So the LPM is designed to be composed of a pair of flat-type stators and a ladder-like robot arm corresponding to the floating mover so that it can be compensated for the resultant decrease of the ratio of thrust to mover mass. The validity of this approach is examined by the static thrust measurements for a tested LPM, and confirmed through the experiments on the robot arm transfer with a magnetic suspention system.

Postchemical‐Mechanical Planarization Cleanup Process for Interlayer Dielectric Films

This paper details postchemical‐mechanical planarization cleanup process development for interlayer dielectric films. The scope of the paper includes defining a base line polish process and developing a post‐CMP cleanup process using 150 mm wafers. The efficiency of the cleaning process was evaluated by the number of (≥0.2 μm) particles remaining on the wafer surface. The cleanup strategy included use of wet wafer transfer, postpolish buffing and rinse, basic chemistry, surfactants, HF, megasonics, and double‐sided scrubbers. Postpolish buffing and rinsing were performed on the polisher. The optimized megasonic process used dilute as the cleaning chemistry. To optimize the mechanical work done on the wafer surface during scrubbing, brush rotation speed, wafer rotation speed, brush height (force), and cleaning time were varied on both the scrubbers. Basic chemistry was used only in the OnTrak scrubber. Dilute and DI water were chosen for the optimized OnTrak and Dai Nippon Screen (DNS) processes, respectively. All the HF work was performed on the DNS scrubber. The overall conclusion is that the polisher plays a major role in achieving low particle levels. Postpolish buffing and high pressure DI water spindle rinse at high spindle rotation after polish are critical for particle reduction. Optimized cleaning processes using either of the double‐sided scrubbers or using the batch megasonic cleanup followed by either of the double‐sided scrubbers provided comparable particle performance. HF was effective in the removal of ionic and metallic contaminants, but further investigation is required to check possible improvement in particle performance.

Low thermal budget in situ cleaning and passivation for silicon epitaxy in a multichamber rapid thermal processing cluster tool

In this Letter, we report our results on surface preparation, involving in situ cleaning and passivation for low-temperature Si epitaxy in a multichamber cluster tool. The experiments were carried out in a three-chamber reactor which mimics a cluster tool. The results indicate that residual O on the dilute HF-treated Si surface (ex situ cleaned) can be reduced below the detection limit of secondary ion mass spectroscopy (SIMS) by in situ baking at 750°C for 15 s in an ultra-high vacuum environment or in H 2 ( pressure = 240 mTorr). We show that the extremely reactive Si surface can be passivated against recontamination by exposing it to a low-pressure Si 2H 6 environment at the ambient temperature immediately following the in situ clean. When the unpassivated samples are exposed to an air pressure of 10 −6 Torr in the load-lock, O adsorbs on the surface up to 50% of a monolayer within 10 min. Under the same conditions, with passivation, the oxygen levels remain below the detection level of SIMS. Surface passivation will be extremely useful in applications that require wafer transfer between chambers such as in multichamber cluster tools.

Film interface control in integrated processing systems*

A number of system concepts in which the integrity of substrate surface and film interfaces are preserved are discussed. This includes stand-alone tools with internal clean air or nitrogen facilities with wafer transfer between such tools in clean containers (‘‘minienvironments’’) and single-wafer and batch-type cluster systems in which the processing and wafer transfer modules are physically connected. Depending on the cleanliness requirements, wafer transfer and processing are done in pure atmospheric nitrogen, low-pressure nitrogen, or vacuum. An analysis is given in which the ambient requirements are related to surface reactivity, wafer transfer time, and acceptable surface contamination level. Trade-offs in terms of capital cost, throughput, flexibility, and film quality are analyzed. A number of different system concepts combining wafer preclean, thin oxide growth, and poly-Si deposition processes are analyzed in terms of their economical performance. It appears that single-wafer systems have a logistic advantage in terms of short cycle time and wafer inventory; however, the cost per wafer of batch-type systems is considerably lower than single-wafer ones. It is shown that the optimum choice between (fast, high-temperature) single-wafer and (slow, low-temperature) batch-type systems in terms of process performance depends on physical parameters such as activation energy and the occurrence of undesired, competing, processes.

In-Process Diagnostic System for Semiconductor Materials Using UHV Wafer Transfer Chamber

AbstractWe have developed a novel stand-alone diagnostic system that can analyze a semiconductor wafer surface in each process without introducing contamination. This allows us to analyze the relationship between chemical conditions and device properties.A UHV (Ultra High Vacuum) wafer transfer chamber is used between the measuring apparatus and the semiconductor processes. The chamber vacuum system, which consists of a battery driven ion pump and a liquid N2 shroud, achieves a pressure of 2 × 10−8 Pa (corresponding to about 100 min. until one monolayer of contamination has been adsorbed).Wafer transfer lines have been constructed between semiconductor vacuum processes, CVD (Chemical Vapor Deposition) and measuring instruments, ESCA (Electron Spectroscopy for Chemical Analysis) and TEM (Transmission Electron Microscope). Our results from ESCA and TEM showed measurements that carbon contamination and oxidation was suppressed.

Integrated processing for microelectronics science and technology

This paper is a review of integrated processing-an approach to microelectronics fabrication in which sequential processes are linked by wafer transfer through a clean, controlled environment (e.g., high vacuum or inert gas). The approach is rapidly becoming the state of the art in microelectronics research, development, and manufacturing. In microelectronics research, it provides a means for advancing mechanistic understanding and material quality through in situ fabrication of test structures and extensive in situ diagnostics. In microelectronics development and manufacturing, it promises process simplification, improved contamination control and yield, and potentially more flexible equipment utilization. With increasing emphasis on ultraclean processing, involving control of reactive impurities as well as particles, and on real-time process monitoring and control, applications of integrated processing are moving toward a common ground in which state-of-the-art research techniques can be used to address key issues in development and manufacturing, and provide in return substantive guidelines for manufacturing design and practice.

Simultaneous deposition and fusion flow planarization of borophosphosilicate glass in a new chemical vapor deposition reactor

Borophosphosilicate glass (BPSG) is an essential dielectric material in the fabrication of advanced silicon gate metal-oxide-semiconductor integrated circuits to planarize the device contour by thermal fusion flow. Chemical vapor deposition (CVD) and fusion anneal are normally performed in separate furnaces, requiring wafer transfer and potentially harmful exposure to ambient air. A new one-step, surface-controlled process allows simultaneous low pressure CVD (LPCVD) and void-free trench filling of narrow trenches with high aspect ratios and surface planarization of ultralarge-scale integrated silicon devices. The process is based on tetraethoxysilane chemistry and is conducted in a LPCVD production reactor of novel design in the temperature range 800–875 °C in less than 15 min. The new process integrates deposition, fusion flow, and anneal; it offers significant advantages over conventional CVD and flow processes in terms of the time-temperature budget and the chemical stability of the resulting BPSG films.

Ultraclean, integrated processing of thermal oxide structures

Ultraclean, integrated metal-oxide-semiconductor oxide fabrication has been investigated for the first time by combining (i) surface cleaning in inert ambient, (ii) wafer transfer through ultrahigh vacuum, and (iii) thermal oxidation in an ultrahigh vacuum-based reactor. Device quality oxide structures are obtained (evidenced by dielectric breakdown characteristics for Al gate capacitors) under suitable conditions, while under other circumstances chemical mechanisms severely degrade electrical performance; even in ultraclean environments, impurity-related Si etching reactions before oxidation degrade oxide quality, but this can be avoided by appropriate use of passivating oxide films which prevent roughness associated with etching.

Contamination-free transfer of silicon wafers with a magnetic levitation transport system in vacuum

A magnetic levitation transport (MLT) system in vacuum has been developed. The system can carry silicon wafers into a number of process chambers for LSI fabrication under particle-free conditions. Since there are no sliding mechanical parts in this system, it does not need lubricants. Therefore, the transport system is free from oil and has a long lifetime. We measured the contamination of dust particles on silicon wafers when the wafers were transferred in vacuum with the MLT system. In this paper, we describe the MLT system and present the results of dust particle measurements.

Vacuum mechatronics and self-contained manufacturing for microelectronics processing

A self-contained automated robotic factory (SCARF) is described. This includes a central chamber with various transfer and monitoring ports, a vacuum-compatible robot for wafer transfer, and a particle monitoring system, all under automation. The cylindrical coordinate SCARF vacuum-compatible robot is unique, due to its fully vacuum-compatible motors, closed-loop control and configuration which makes it an ideal central component for a self-contained manufacturing system. Color vision system for in-vacuum inspection and measurement which will be an integral part of SCARF is being developed. Details of the SCARF system and robot are discussed, as well as the key technical issues facing the development of self-contained manufacturing systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Development of an ultrahigh vacuum, i n v a c u o wafer transfer facility integrated processing

An ultrahigh vacuum, in vacuo wafer transfer system has been completed for development of integrated wafer processing. Design decisions which determined the structural layout and the interior design of the vacuum transfer vessel are elucidated in this paper. Among the criteria considered were (i) the areal floor space occupied by the transfer device, (ii) the average travel distance per transfer, and (iii) an awareness that mechanical function must be incorporated without leading to wafer particulate contamination. Of these criteria, the first two influenced the structural arrangement of the transfer system while the last criterion influenced the interior design. Elementary calculations are presented for a simple rotary and linear transfer tube design. These calculations show that, for integration of more than four nodes, the linear transfer design occupies less floor space than a rotary design would occupy. Calculations show that the rotary design does offer a shorter average transfer distance. However, trafficking of the process steps will produce comparable average travel distances per transfer between the rotary and linear designs. To reduce wafer particulate contamination, the interior design included face-down susceptors in all deposition chambers, vertical wafer storage, isolation valves off line from the linear transfer, and concealed gear trains. The vacuum transfer vessel currently interconnects a chemical vapor deposition unit, a surface analytical unit, a substrate modification chamber, a molecular-beam epitaxy chamber, and a vertical load lock. Vacuum performance curves for samples entering the transfer vessel from air show that water desorption from the sample carrier and wafer must be enhanced during sample entry into the transfer system; else, water desorption can inadvertently occur during subsequent processing steps.

Photolithography in an open area environment: The OASIS project

The S tandard M echanical I nter F ace (SMIF) provides a convenient way to handle wafers outside the cleanroom with no added contamination. In this approach each piece of process equipment is enclosed in a clean chamber fitted with special ports for wafer ingress and egress. The wafers themselves are moved between work stations in small enclosures (“SMIF boxes”), specifically designed to exclude airborne particulate contamination from the outside environment; the SMIF boxes and the equipment input-output ports are engineered to prevent contamination during wafer transfer. The motivation for developing this concept as an alternative to the lithographic module ( O pen A rea S MIF I solation S ite, or OASIS) was built, using the SMIF interfacing concept in an open area, defined as a normal office environment. The various tasks which this project entailed are described, as well as the methods used to evaluate the quality of the photolithographic process. The results achieved to-date are briefly reviewed; they show that cleanliness equivalent to that obtained in a cleanroom could be achieved in the OASIS processing module, though it is operated in an open area. While these results cannot be readily extrapolated to a complete mass production facility, it appears that no major difficulties would impede the construction and operation of a complete manufacturing line, without the need for a cleanroom.

A Microprocessor-Based Architecture for E-Beam Wafer Transfer System

Moving wafers from atmosphere into a high vacuum chamber and onto an X-Y stage in a system whose primary objective is high throughput can be a challenging undertaking. Position sensing of mechanisms, tolerance to transients and switching noise, flexibility to modify operating modes, extensive diagnostic capability, and a user-friendly set of controls are but a few of the considerations to be made in such a transfer system. Since this is a production tool, reliability and serviceability must be carefully designed into the system from the start. Fail-safe operation is also a necessity and is accomplished through built in interlocks and software routines, however, the inclusion of a failsafe operating system does not preclude the need for failure recovery capability. Although the ultimate objective is to maintain continuous system operation through automatic failure recovery procedures, the control system must provide an unambiguous status of the operation when it cannot recover and requires manual intervention. This is particularly true with an internal wafer transfer, since the operation is invisible and fairly inaccessible to an operator. The architecture to be described accommodates these needs using distributed microprocessor control. The major functions under processor control include vacuum and wafer transfer control, elevator, and transfer arm motor control. Access to this system is via an IBM PC. A larger function done by a single 16-bit microprocess is that of interfacing with an IBM Series 1 computer, which controls an entire E-Beam system. The objectives of this architecture are the following: · separate control functions for greatest efficiency · provide operational flexibility · maximize diagnostic capability by enhancing the operator interface · automate failure recovery using more extensive data evaluations · reduce sensor requirements through quick evaluation of more input data · enhance noise immunity · increase reliability by using standard functional circuitry and microprocessor control.

Design and evaluation of wafer transfer system for LSI production

AbstractAn automatic wafer transportation system has been developed that is suitable for the LSI fabrication line. Design objectives have been to achieve a flexible wafer routing and flexible line construction ensuring a high degree of cleanliness. The system consists of a computer‐controlled carriage system carrying wafer cassettes on a ceiling track, and standardized interface mechanisms installed on each equipment. This paper describes technical factors involved in the realization of flexible lines, and considers also fundamental track arrangement, carriage characteristics, a wafer‐routing control method, and low dust mechanisms.

Wafer transfer system for LSI production.

64 Kbit RAM mass-production indicates the beginning of VLSI age. And moreover, 256 Kbit RAM is being shipped. It is needed to achieve a high-cleanliness production environment and to accomplish a total process automation for the increase of VLSI products. This paper deals with a low dust carriage system for LSI wafer transfer. The great part of dust is caused by power collector mechanism and drive mechanism on an usual carriage. Then, the power collector mechanism and the drive mechanism were investigated. The investigation revealed that a low dust carriage system was able to be realized by the adoption of a rolling contact type collector and a flexible steering mechanism.