Wafer Thickness Research Articles

PLA Renewable Bio Polymer Based Solid-State Gamma Radiation Detector-Dosimeter for Biomedical and Nuclear Industry Applications.

Polylactic acid (PLA) as a "green," renewable corn-soy based polymer resin was assessed as a novel solid-state detector for rapid-turnaround gamma radiation dosimetry in the 1-100 kGy range-of significant interest in biomedical and general nuclear industry applications. Co-60 was used as the source of gamma photons. It was found that PLA resin responds well in terms of rheology and porosity metrics with an absorbed gamma dose (Dg). In this work, rheological changes were ascertained via measuring the differential mass loss ratio (MLR) of irradiated PLA placed within PTFE-framed (40 mm × 20 mm × 0.77 mm) cavities bearing ~0.9 g of PLA resin and pressed for 12-16 min in a controlled force hot press under ~6.6 kN loading and platens heated to 227 °C for the low Dg range: 0-11 kGy; and to 193 °C for the extended Dg range: 11-120 kGy. MLR varied quadratically from 0.05 to ~0.2 (1σ ~ 0.007) in the 0-11 kGy experiments, and from 0.05 to ~0.5 (1σ ~0.01) in the 0-120 kGy experiments. Rheological changes from gamma irradiation were modeled and simultaneously correlated with void-pocket formations, which increase with Dg. A single PLA resin bead (~0.04 g) was compressed 5 min at 216 °C in 0-16 kGy experiments, and compressed 2 min at 232 °C in the 16-110 kGy experiments, to form sturdy ~100 µm thick wafers in the same press. Aggregate coupon porosity was then readily measurable with conventional optical microscope imaging and analyzed with standard image processing; this provided complementary data to MLR. Average porosity vs. dose varied quadratically from ~0 to ~15% in the 0-16 kGy range and from ~0 to ~18% over the 16-114 kGy range. These results provide evidence for utilizing "green"/renewable (under $0.01) PLA resin beads for rapid and accurate (+/-5-10%) gamma dosimetry over a wide 0-120 kGy range, using simple to deploy mass and void measuring techniques using common laboratory equipment.

N-type diamane: An effective emitter layer in crystalline silicon heterojunction solar cell

In the presented work, cell's parameter of heterostructure silicon solar cell modelled as: ITO (front contact)/n-Dn/p-cSi/Ag under the illumination of monochromatic light at standard spectrum AM-1.5 G, has been optimized by using AFORS-HET v 2.5 software. We have used n-type diamane as an emitter layer and the nature of diamane has been considered 3D in spite of 2D as well as electronic nature of diamane is considered isotropic. To ensure that Schottky junction has been formed at interface, the electric contacts have been made along the c-axis so that maximum charge carriers get collected. To obtain the high efficiency, various parameters of n-type diamane as well as p-type c-Si layers have been optimized and the maximum efficiency of 16.84% has been obtained for single layer n-diamane at 100 µm thick silicon wafer. We also investigated the spectral response and dependency of temperature on the performance of exclusively designed solar cell and we obtained the best efficiency 16.84% at 300 K temperature. In order to check the performance on commercially available silicon we have optimized the same solar cell by considering the parameters of commercially available p-type crystalline silicon layer and maximum efficiency 10.41% was achieved. After getting the maximum efficiency 16.84% we further carried out the simulation by optimizing the layer numbers of n-diamane and found decrement in the efficiency up to 15.3% which indicates that, efficiency slightly decreases as layer number increases. We have demonstrated that n-type diamane might be used as an effective emitter layer in crystalline Si heterojunction solar cell.

Characterization of Defects in GaN: Optical and Magnetic Resonance Techniques

GaN and its alloys with InN and AlN are of technological importance for a variety of optical, electronic, and optoelectronic devices due to its high thermal conductivity, wide band gap, high breakdown voltage and high saturation velocity. GaN-based devices now provide superior performance for a variety of high power, high frequency, high temperature, and optical applications. The major roadblock for the full realization of Nitride semiconductor potential is still the availability of affordable large-area and high-quality native substrates with controlled electrical properties. Despite the impressive accomplishments recently achieved by techniques such as hydride vapor phase epitaxy and ammonothermal for GaN growth, much more must be attained before establishing a fully satisfactory bulk growth method for this material. Recent results suggest that ammonothermal GaN wafers can be successfully used as seeds to grow thick freestanding GaN wafers by hydride vapor phase epitaxy. A brief review of defect-sensitive optical and paramagnetic spectroscopy techniques employed to evaluate structural, optical, and electronic properties of the state-of-the-art bulk and thick-film (quasi-bulk) Nitride substrates and homoepitaxial films is presented. Defects control the performance of devices and feeding back knowledge of defects to growth efforts is key to advancing technology.

Gross fracture pits at the intersection of two single scratches during grinding of silicon

Infeed grinding is used in the industry for grinding thick silicon wafers. The grinding process being a series of overlapping scratches, leaves behind the surface and sub-surface damages in the silicon. Continuous in-feed grinding of a thick wafer when used to produce thin wafer leads to breakage upon release from the fixture. This happens because of not only damage induced by a single scratch, but also due to cumulative damage induced as the grinding proceeds with several overlapping and intersecting scratches. In a single scratch, depths below a critical depth can cause material removal without gross fracture and pits; however, it is not clear if this applies to multiple intersecting scratches while grinding silicon. In this study, the grinding operation is performed for a very short period of time, gradually removing the material over only a partial region of the wafer surface while leaving the remaining portion unground. This produces multiple intersecting grinding scratches of increasing depth. Scanning electron microscopy and surface profile measurements of these scratches show that while in a single scratch, material is removed without gross fracture and pitting; when two such scratch intersects, it results in gross fracture at the site of their intersection. Such gross fractures at intersections can happen even at a very shallow depth of scratch as low as 28 nm. This gross fracture at the intersections act as local sites to initiate wafer damage and material removal. Based on the results, we attempted to redefine the critical depth of cut for grinding operation. The study paves the way to manufacture thin damage-free wafers needed for the next generation thin silicon solar cells.

Response testing of Schottky-barrier GaAs detectors with alpha particles

The development of new radiation detectors for harsh environments relies on the study of different materials and processes. In this work Gallium arsenide Schottky-barrier detectors were produced by thin film deposition on 500 μm thick GaAs wafers. Several tests of enclosure were made, and best results were obtained using commercial SSB detector fixture. Testing with NIM electronics and 241 Am alpha-particle source were made to obtain the characteristics of produced detectors. Simulations have shown that GaAs devices are resistant to ion radiation, however signal-to-noise ratio must be improved.

Ray Tracing of Thin PERC Silicon Solar Cells with Cone Textures

Thinning of crystalline silicon (c-Si) wafer is a promising approach to reduce the technology cost of passivated emitter rear cell (PERC) solar cell. However, reducing the wafer thickness compromises light absorption, hence short-circuit current density (Jsc) in the solar cell. This necessitates effective light trapping in the device. In this work, upright cone textures are incorporated on the surface of 50 μm PERC monocrystalline silicon solar cell. SunSolve ray tracer is used to simulate the optical and electrical properties of the solar cell within 300-1200 nm wavelength region. Besides, the solar cell is also simulated with a front silicon nitride (SiNx) anti-reflective coating (ARC) on the cone textures. From the results, the thin PERC solar cell with cone textures and SiNx ARC demonstrates Jsc of up to 38.8 mA/cm2 and conversion efficiency of 20.4%. This is a significant performance improvement when compared to the planar cell, with Jsc of 25.1 mA/cm2 and efficiency of 13.1%. The improvement is attributed to the enhanced broadband light absorption and increased external quantum efficiency in the device.

Ultrathin single-crystalline perovskites: Toward large area wafers

The growth of large-area ultrathin single-crystalline wafers of methylammonium lead bromide is investigated on a hole transport layer using a diffusion-facilitated inverse temperature crystallization method. It is shown that, in addition to the hydrophobic confining layers, optimized precursor molar ratio and growth temperature are essential for realizing large-area single-crystalline wafers of device-friendly thickness in the range of 20–30 µm. The necessity of the hydrophobic layer for the realization of large-area wafers using the space confined crystal growth method is explained from consideration of the occurrence of heterogeneous nucleation. Space-charge limited current studies of the device fabricated with the synthesized single-crystal wafer show excellent charge transport mobility of 2.12 cm2/vs and a low trap-state density of 1.34 ⋅ 1011 cm−3.

Impacts of hydrogen annealing on the carrier lifetimes in p-type 4H-SiC after thermal oxidation

Thermal oxidation and hydrogen annealing were applied on a 100 μm thick Al-doped p-type 4H-SiC epitaxial wafer to modulate the minority carrier lifetime, which was investigated by microwave photoconductive decay (μ-PCD). The minority carrier lifetime decreased after each thermal oxidation. On the contrary, with the hydrogen annealing time increasing to 3 hours, the minority carrier lifetime increased from 1.1 μs (as-grown) to 3.14 μs and then saturated after the annealing time reached 4 hours. The increase of surface roughness from 0.236 nm to 0.316 nm may also be one of the reasons for limiting the further improvement of the minority carrier lifetimes. Moreover, the whole wafer mappings of minority carrier lifetimes before and after hydrogen annealing were measured and discussed. The average minority carrier lifetime was up to 1.94 μs and non-uniformity of carrier lifetime reached 38% after 4-hour hydrogen annealing. The increasing minority carrier lifetimes could be attributed to the double mechanisms of excess carbon atoms diffusion caused by selective etching of Si atoms and passivation of deep-level defects by hydrogen atoms.

Growth of ZnTe Semiconductor Crystal Via a Te Flux Zone Melting Method and Characterization of Its Properties

AbstractIn this work, a kind of II;‐VI group ZnTe semiconductor crystal is successfully grown using a Te flux zone melting method from Zn: Te = 3: 7 mole ratio solution. The crystal has standard F43m cubic space group and the a/b/c lattice constants are all calculated to be 6.105 Å. Energy dispersive spectroscopy analysis confirms it has quasistoichiometric ratio and the Zn/Te elements are distributed in the material homogeneously. The polished 1.0 mm thickness (110) wafer exhibits a highest ≈64.5% transmittance near 2400 nm wavelength and the bandgap Eg is deduced as 2.223 eV. ZnTe crystal shows a heavy volatilization start from 910 °C and the weight losing speed is about ≈1.45% min−1. The thermal conductivity k displays good repeatability in the cooling and heating stages, the k value is about 15.8 Wm−1 K−1 at room temperature and is deceased to 3.53 Wm−1 K−1 under 500 °C. These results would be of great reference when ZnTe crystal is used for device design and application in the future.

Performance Measurements of Photodiodes for X-Ray Detection

The X-ray free-electron laser (XFEL) at the Pohang Accelerator Laboratory (PAL), Pohang, South Korea, provides X-ray energies of up to 15 keV depending on the experimental purpose. Silicon-based devices have been used as diagnostic devices and detectors for X-rays in experimental stations. Considering recent domestic and international circumstances, developing silicon-based detectors in-house is necessary. We developed a silicon p-intrinsic-n (PIN) photodiode (PD) for X-ray detection, and its performance was investigated and compared with that of a commercial PD used in the PAL-XFEL. The PD was designed to be 1 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1$ </tex-math></inline-formula> cm in size, and it used the junction side for signal readout and the ohmic side for X-ray entrance. Considering the absorption length of 12-keV X-rays suitable for crystallography, a 500- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\mu }\text{m}$ </tex-math></inline-formula> -thick silicon wafer with a high resistivity was used for PD fabrication. It has a guard ring, an n+ edge field shaper, and an antireflection coating (ARC) and is available in four different types based on the metal structure of the junction and ohmic sides. We present here the electrical characteristics of the PDs. The depletion voltage at which the bulk of the PD is fully depleted was determined to be 119.7 ± 8.2 V from bulk capacitance measurements, and the operation voltage of the PD was set to 200 V. PDs with leakage currents less than 30 nA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the operation voltage were chosen for performance measurements. The signal-to-noise ratio (SNR) with a Sr-90 radioactive source corresponding to the minimum ionizing particle (MIP) and the quantum efficiency (QE) for wavelengths of 300–1000 nm were measured. Beam tests were conducted at the PAL-XFEL using 600-, 900-, and 1200-eV X-rays where the responses to ultrahigh brightness and ultrashort X-ray pulses were checked. The energy resolutions were measured using gamma-ray radioactive sources, Am-241 (59.5 keV), and Ba-133 (31.0 and 81.0 keV). The differences in performance among the PD types are presented herein in terms of the electrical characteristics, SNR, QE, response to X-ray pulses, and energy resolutions. The results of the fabricated PDs were also compared with those of a commercial PD.

Development of Low Temperature Double Level TSV, Hole and Seal Process for Low Pressure Zero Level MEMS Packaging

Through Silicon Via (TSV) technology is considered one of the key methods to enable heterogeneous integration at the third dimension and realize electrical interconnection between device parts. In that context, different components (MEMS, sensors, circuits etc.) can be electrically integrated in 3D manner, increasing stack density, shrinking footprint, and reducing fabrication costs. At MEMS integration, it is important to explore the packaging method that enables the optimum performance of the active MEMS component and the TSV approach to electrically connect it with the package. Herein, we present our via-last approach to integrate a zero-level packaged MEMS wafer defined by cavity SOI (C-SOI) and CMOS readout circuitry (at thermal budget <400ºC). TSV distribution and fabrication route ensures the electrical connectivity of MEMS inertial sensor and CMOS. Furthermore, a hole is added to the layout scheme and sealed afterwards to ensure low pressure encapsulation in the MEMS cavity.In our previous work related to MEMS fabrication [1], we elaborated the superiority of C-SOI start material over conventional fabrication methods (like vapor HF). In our approach, MEMS cavity structures are realized by patterning dielectrics and the moving parts by employing deep Si etch (DSiE) method (Fig 1 a-c). To enhance the dielectric surface smoothness prior bonding, a complementary HF -based clean applied. This way, bonding requirements (Rq<1nm, Rrange<10nm) are met. CMOS wafer is fabricated with a single layer of Cu damascene process in a dielectric stack to create complementary bonding medium for MEMS wafer. Selected dielectrics at MEMS (thermal oxide) and CMOS (SiCN) can perform better at low temperature fusion bonding due to their moisture blocking capability. Next, fusion bonding at room temperature is carried out using assisted force (60kN) to enhance bonding efficiency and completed by curing the wafer pair at 350˚C.In this paper, we present further work to complete the MEMS zero-level packaging through electrical connections and vacuum seal. Fabrication sequence continues on the backside of the MEMS wafer (Fig 1d-g). First the desired top membrane (cap) thickness of MEMS wafer realized by thinning bulk Si substrate down to 50µm. After SiOx deposition, a double TSV approach is carried out aiming to create the electrical interconnections between the package components, one to reach to the sensor parts in MEMS wafer and one to reach to CMOS. TSV for enabling the connection with sensor parts (12x50μm) is realized by DSiE through the top Si membrane and buried oxide (BOX) landing at Si epi layer of C-SOI. Isolation of this TSV is obtained by conformal liner deposition using SACVD SiOx (350C). Liner opening at the TSV base is assisted by a second non-conformal dielectric deposition to protect the sidewall isolation during resistless directional liner etch back at TSV bottom. Metallization of the via is carried out by sequential PVD barrier (Ta) and seed (Cu) depositions; and the TSV is filled with electroplated Cu. MEMS top surface is then cleared either by CMP or by wet and dry etching of Cu and Ta, respectively. TSV for connecting to CMOS (20x80μm) follows the same processing route with an additional DSiE through all the C-SOI MEMS stack and landing on designated plugs on CMOS. With these two TSV schemes it is ensured to bias and measure the inertial sensor, its driving circuitry, and the zero-level package (Fig. 2a)Once the two TSVs fabrication is completed, hole for the vacuum sealing can be created. First, the top dielectric on surface of MEMS wafer is etched in circular areas of diameter 10μm to define where the venting holes will be created. This is mainly to expose Si surface and reduce possible leakage paths, as well as to increase the adhesion of the deposited metallization to close the hole under vacuum. Small hole (Ø2μm) is defined in the middle of the Si circular area by lithography and etching through the top MEMS membrane (50μm) landing on the cavity of the C-SOI (Fig 1f). Vacuum seal of the zero-level package is finalized with bond pad creation which also seals the hole under vacuum. Al deposition is carried out at high vacuum PVD system; the hole is simultaneously sealed and preserve the same vacuum as the PVD chamber. Along with the chamber vacuum level, the Al thickness and power is also very important to achieve the desired seal Fig.2b.Proposed work enables zero-level MEMS hermetic packaging with integrated CMOS and developed on 200mm wafers.[1] Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging, A.Malainou, J.Visker, D.Sabuncuoglu, 21st EPTC, Singapore 2019 Figure 1

Simplified Recovery Process for Resistive Solder Bond (RSB) Hotspots Caused by Poor Soldering of Crystalline Silicon Photovoltaic Modules Using Resin

When the thickness of the solar cell wafer and the amount of Ag to be used decreases, it is the best method to recover the power of the module after use at a minimum cost and reuse the module itself. Economic recovery technology can be applied to the power degradation, caused by the resistive solder bond (RSB) hotspot by poor soldering, because the recovery process can be simplified compared to the power loss that is often greater than 30%. This study demonstrated a quick recovery of the RSB hotspot with on-site recovery technology applied with resin and verified the performance and long-term reliability of on-site recovery technology, compared to the factory recovery method, where the back sheet is removed and laminated to recover the module. Both the factory and field recovery methods confirmed recovery results closer to the initial rated power output of the samples. Each sample was degraded by the RSB hotspot to ~62–65% of the initial power output, and the recovery process successfully recovered it to ~96–99%. In on-site recovery, verification of the possible EVA solvothermal swelling, which is the effect of organic solvents contained in the resin on EVA, is essential for verifying the long-term reliability of the recovered module. In this study, the power degradations of the on-site recovered samples after a TC 200 cycle test are −2.14% and −0.95%, respectively, which are within the certification test standard of the new manufacturing module. Existing factory recovery costs not only in the recovery process, but also in a total of 22 stages, such as the transfer of the target module. The largest advantage is that the on-site recovery process can be restarted in the field after only eight stages.

An Investigation on the Total Thickness Variation Control and Optimization in the Wafer Backside Grinding Process.

The wafer backside grinding process has been a crucial technology to realize multi-layer stacking and chip performance improvement in the three dimension integrated circuits (3D IC) manufacturing. The total thickness variation (TTV) control is the bottleneck in the advanced process. However, the quantitative analysis theory model and adjustment strategy for TTV control are not currently available. This paper developed a comprehensive simulation model based on the optimized grinding tool configuration, and several typical TTV shapes were obtained. The relationship between the TTV feature components and the spindle posture was established. The linear superposition effect of TTV feature components and a new formation mechanism of TTV shape were revealed. It illustrated that the couple variation between the two TTV feature components could not be eliminated completely. To achieve the desired wafer thickness uniformity through a concise spindle posture adjustment operation, an effective strategy for TTV control was proposed. The experiments on TTV optimization were carried out, through which the developed model and TTV control strategy were verified to play a significant role in wafer thickness uniformity improvement. This work revealed a new insight into the fine control method to the TTV optimization, and provided a guidance for high-end grinding tool and advanced thinning process development.

Reduced On-Resistance and Improved 4H-SiC Junction Barrier Schottky Diodes Performance by Laser Annealing on C-Face Ohmic Regions in Thin Structures

In this study, we investigated the characteristics of the n-type Ni/SiC ohmic contact using the laser annealing process on thin wafers. The electrical behavior of the ohmic contacts was tested in 4H-SiC JBS diode devices. As a result, a wafer thickness of 100 μm in the 4H-SiC JBS diode achieved a forward voltage of 1.33 V at 20 A with a laser annealing process using Ni silicide. Using a laser annealing process on a wafer thickness of 100 μm, an on-resistance decrease of almost 22% was demonstrated. Based on our experimental results, we suggest an alternative laser annealing fabrication scheme to obtain low on-resistance SiC power devices with thin structures after SiC grinding.

On the use of sacrificial layer in ECDM process for form accuracy

During the electrochemical discharge machining (ECDM) process, major imperfections on work material occurs due to stray cutting caused by thermal energy. Some of these are re-solidification, melt flow over, thermal splashes, micro-cracks, work material breakage, hole over cut (HOC), and sudden taper. These thermal deteriorations are inherent in thermal-based processes like the ECDM process. Post-processing of these machined features at micron-level on glass material is a challenging task. To overcome this issue, in the present article, the depth up to which thermal damages occurred was predicted at given input energy conditions and the same thickness of glass wafer was bonded over the work material during machining. In order to find out the thickness, a pressurized tool feeding and dial gauge attachment was designed. Using this attachment, instantaneous depth was measured at every second of machining time and effective energy supplied to each plane of the work material was calculated analytically. The same was imported in to COMSOL Multiphysics software for simulating the heat flux gradient and temperature distribution on each plane of the work material. Using the simulation data, the depths from the hole entrance that are more prone to thermal deteriorations was identified. This depth was considered as critical depth for respective input energy conditions. Applied voltage, pulse on time, and glass wafer thickness were considered as input parametric conditions, and machined hole depth, HOC, and hole quality on work material were considered as output characteristics. Experiments were performed with various parametric conditions, and it was observed that the glass wafer carried away the major thermal deteriorations and leaving minimal damages on the work material. At the optimal parametric conditions, HOC was reduced by 71.5% and hole quality was improved significantly. Application of glass wafer compromises around 39% hole depth.

Towards 28 %-efficient Si single-junction solar cells with better passivating POLO junctions and photonic crystals

We conduct numerical device simulations to study to what extend poly-Si on oxide (POLO)2 IBC solar cells can be optimized. In particular, we evaluate the benefit of the concept of photonic crystals (PCs) for “standard” cell thicknesses compatible with industrial wafer handling. We find that for our current surface passivation quality, implementing PCs and decreasing the wafer thickness down to 15 μm would increase the efficiency by „only“ 1% absolute due to limiting surface recombination losses. We deduce a high c-Si/SiOx interface state density Dit of 2.9 × 1012 eV−1cm−2 by analyzing special two-terminal IV measurements on small pads that contact the intact interfacial oxide between pinholes with our MarcoPOLO model. Consequently, we improve the hydrogenation process of our POLO junctions by an Al2O3/SiNx/Al2O3 rear-side dielectric layer stack. For n-type POLO (p-type POLO) J0 is reduced from 4 (10) fA/cm2 down to 0.5 ± 0.3 (3.3 ± 0.7) fA/cm2. For this improved surface passivation, our numerical device simulations predict an efficiency potential of 29.1% (27.8%) for POLO2 IBC cells with (without) PCs for a standard thickness of 150 μm. This shows that the “practical limit” for Si solar cells with poly-Si on oxide-based passivating contact schemes is above 27%, and, in general, that the efficiency potential of Si single-junction cells is still far from being exhausted. The first implementation of the improved POLO junctions into cell precursors confirms the predicted improvement on the level of suns - implied open-circuit voltage curves.

Global prediction of the energy yields for hybrid perovskite/Si tandem and Si heterojunction single solar modules

AbstractA strong expectation exists for a two‐terminal hybrid perovskite/silicon tandem solar cell for generating substantially higher output power. Nevertheless, a high tandem cell efficiency under the standard condition does not guarantee high power generation in outdoor environment due to the requirement of current matching in a tandem device. Here, we predict the global energy yields of hybrid perovskite/Si tandem and Si heterojunction single modules by establishing a new rigorous self‐consistent model that performs full device simulations incorporating all fundamental time‐varying parameters affecting the module power output. In particular, the temperature dependences of the optical and electrical characteristics are modeled explicitly and reliable model parameters are extracted from an industry‐compatible Si heterojunction single cell (23.27% efficiency with a 120 μm wafer thickness), whereas ideal cell characteristics are assumed for a hybrid perovskite top cell. Our simulation approach is justified from the remarkable agreement with experimental results. We find that the tandem architecture improves a module energy yield in all places by a maximum of 1.6 times, compared with a state‐of‐the‐art Si heterojunction single module. Importantly, the annual energy yields of the tandem and single modules scale linearly with annual sun irradiation, even with the requirement of the current matching in the case of the tandem device, and the ratio of the tandem and single energy yields is governed essentially by the module efficiency ratio obtained under standard conditions. We have further revealed the climate‐dependent energy yield variation with a magnitude of ~5% based on Köppen‐Geiger climate classification. Moreover, the optimization of the top‐cell band gap based on real meteorological data shows that the optimum top‐cell gap needs to be increased at a place with a lower solar irradiation.

Effect of capillary adhesion on fracture of photovoltaic silicon wafers during diamond wire slicing

As the photovoltaic industry needs to reduce manufacturing costs, the kerf loss and the wafer thickness of diamond wire slicing will be further reduced in the future, which will make the spacing and bending rigidity of the wafers decrease to the extent that the effect of capillary adhesion of wafers is more significant during slicing, thus increasing the risk of silicon wafer fracture. Therefore, a hierarchical capillary adhesion model of wafers during the diamond wire slicing based on the principle of minimum potential energy is established in this paper. The variation of the maximum bending stress and the number of adhered wafers with sawing depth, kerf width, and wafer thickness and the effect of capillary adhesion on the silicon wafer fracture are studied. The results show that the maximum bending stress and the number of adhered wafers increased with the increase of the sawing depth, which meant that the risk of wafer fracture was greater for sawing large-sized wafers. And they also tended to increase as the kerf width and the wafer thickness decreased, that was, the effect of capillary adhesion on the thin wafer sawn with a fine diamond wire was more significant. In addition, the probability of the mono-Si wafers fracture caused by capillary adhesion increased significantly when the wafer thickness was less than 100 μm. The research work is of great significance for further research on the thin wafers slicing technology with the fine diamond wire to reduce the manufacturing costs of silicon wafers in the photovoltaic industry.

Investigation and multi-objective optimization of monocrystalline silicon wafering using wire electro-discharge machining

Monocrystalline silicon wafers are widely used as the primary material for solar cell production in the photovoltaic industry, owing to their high efficiency and sleeker aesthetic. Wafering is the primary process towards wafer production. The existing wafering processes have limitations of cracking, chipping, and high kerf loss, arising the need for cost-efficient and precise methods to produce wafers. In the present experimental work, an attempt has been made to explore the potential of Wire Electro-discharge Machining (WEDM) for wafer production and to gain an understanding of the effects caused by pulse on time (Ton), pulse off time (Toff), peak current (Ip), wire tension (WT), and wire feed rate (WFR) during the wafering process to achieve the optimal parametric setting for attaining maximum wafering speed and minimum surface roughness. The work material used was P-type monocrystalline silicon. Wafers thickness of 250 μm was produced, avoiding edge chipping. The experimentation was planned according to the face-centered central composite design. The obtained results were statistically analyzed, and response surface methodology (RSM) was used to model the wafering speed and surface roughness. From the analysis of experimental results, it was noticed that at the higher level of Ton and Ip, a maximum wafering speed of 2.574 mm/min was attained. In contrast, the minimum surface roughness of 1.57 μm was achieved at the lower level of Ton and Ip. The most significant process variables that influence the wafering speed and surface roughness are the Ton, Toff, and Ip. Micrographs of the wafer surface reveal the presence of micro craters, but there was no evidence of micro-cracks. The multi-objective optimization of the responses was done using the desirability approach, and the optimized values of wafering speed and surface roughness attained were 0.989 mm/min and 1.57 μm, respectively.

Accurate characterization of surface recombination velocities of silicon wafers with differential nonlinear photocarrier radiometry

The surface recombination velocity (SRV), which reflects the fundamental characteristics of surface defects of semiconductor wafers, is an important parameter in evaluating the quality of surface passivation and electrical performance of surface devices. In conventional photocarrier radiometry (PCR) used for characterizing the electronic transport properties of electronically thick silicon wafers, the rear SRV usually cannot be determined directly due to the relatively low sensitivity of PCR signal to the rear SRV. On the other hand, the determination of front SRV is also very sensitive to the experimental measurement error, especially the measurement error of instrumental frequency response, which is not always easy to be accurately measured in the experiment. In this paper, the front and rear SRVs of silicon wafers are extracted simultaneously with high accuracy by a differential PCR via multi-parameter fitting of the experimental frequency dependences of amplitude ratio and phase difference of PCR signals obtained from the regular measurements and measurements with wafers being flipped respectively to a corresponding differential nonlinear PCR model. The comparison between the front and rear SRVs determined by the conventional and differential PCRs indicates that the differential PCR is highly accurate for the simultaneous determination of the front and rear SRVs of silicon wafers.