Wafer Probe Research Articles

Mechanical Robustness Analysis of Semiconductors with a Single Needle Probe Card Using Acoustic Emissions

The combination of indentation testing and acoustic emission (AE) is widely used to analyze the fracture toughness of test substrates. In the manufacturing of semiconductor devices this material parameter also plays an important role. During the so-called wafer testing inside a wafer prober small probe tips are pressed onto the chip surface to check its performance. To prevent damaging the chip by that, the fracture toughness and load limit of it has to be defined in a prequalification step. This paper presents a test system that imitates the wafer testing process as close as possible and uses acoustic emission to detect appearing cracks and thereby also the load limit. The frontend of the test setup consists of a modular single needle probe card which can be placed in a wafer prober. Also, the indenter properties (tip diameter, stiffness, etc.) can be adjusted to the probe used later on during productive wafer testing to ensure realistic probing conditions. A piezoelectric sensor and a full strain gauge Wheatstone bridge are implemented close to the single indenter to measure the AEs and the applied contact force respectively. The signal-to-noise-ratios (SNRs) of both sensors are improved with an own analog amplifier module before recording them with an USB oscilloscope. A developed measurement software (LabVIEW) is used to adjust measurement parameters (trigger limit, record length, conversion factors, etc.) and automatically store and separate measurement data from different acoustic events and imprints. To evaluate the result files a second software tool (MATLAB) reads the files out and clusters the recorded events to separate crack signals from electrical and mechanical disturbances. With a prototype first test results are generated and the functionality and accuracy of the measurement concept is proven.

200 mm Wafer Level Characterization at 2 K of Si/SiGe Field-Effect Transistors

Si/SiGe has proven to be an excellent spin qubit platform, but industrial production of large-scale spin-qubit chips is missing. We use field effect transistors (FETs) to monitor and develop the quality of the fabrication process on 200 mm wafers at 2 K using a cryogenic wafer prober (CWP). This mass-characterization technique provides statistics on device performance. We observe variations in drain off current and gate threshold voltage of 213 FETs. These variations are related to bias voltage conditions during CWP cooldown, which differ from qubit chip cooldown. To address this, a new FET structure with an additional top gate is introduced, effectively suppressing unintentional charge accumulations. This eliminates drain off currents and improves homogeneity of FET characteristics at 2 K. Our results highlight significant impact of bias conditions during qubit chip cooldown, which, if not accounted for in the qubit chip design, can lead to incorrect conclusions when using CWP.

Advances in Wafer Probing with Ultra-Short Pitch SoCs

The semiconductor industry is in a constant state of evolution, driven by the relentless pursuit of improved performance, enhanced efficiency, and the ever-decreasing size of electronic devices. A critical aspect of this advancement is the development of ultra-short pitch system-on-chips (SoCs). These SoCs, characterized by their densely packed connections and minimal spacing between contact points, present unique challenges during wafer probing—a crucial step in semiconductor manufacturing. This article delves into the complexities of wafer testing for short pitch SoCs, explores the latest innovations in this domain, and discusses how these advancements are revolutionizing semiconductor manufacturing processes.

A Novel Out-of-Control Action Plan (OCAP) for Optimizing Efficiency and Quality in the Wafer Probing Process for Semiconductor Manufacturing.

The out-of-control action plan (OCAP) is crucial in the wafer probing process of semiconductor manufacturing as it systematically addresses and corrects deviations, ensuring the high quality and reliability of semiconductor devices. However, the traditional OCAP involves many redundant and complicated processes after failures occur on production lines, which can delay production and escalate costs. To overcome the traditional OCAP's limitations, this paper proposes a novel OCAP aimed at enhancing the wafer probing process in semiconductor manufacturing. The proposed OCAP integrates proactive measures such as preventive maintenance and advanced monitoring technologies, which are tested and verified through a comprehensive experimental setup. Implementing the novel OCAP in a case company's production line reduced machine downtime by over 24 h per week and increased wafer production by about 23 wafers per week. Additionally, probe test yield improved by an average of 1.1%, demonstrating the effectiveness of the proposed method. This paper not only explores the implementation of the novel OCAP but also compares it with the traditional OCAP, highlighting significant improvements in efficiency and production output. The results underscore the potential of advanced OCAP to enhance manufacturing processes by reducing dependency on human judgment, thus lowering the likelihood of errors and improving overall equipment effectiveness (OEE).

Neural-network-based transfer learning for predicting cryo-CMOS characteristics from small datasets

Transfer learning was examined to predict current-voltage (I-V) characteristics of MOSFETs at cryogenic temperatures. An experimental dataset was obtained from approximately 800 silicon-on-insulator MOSFETs using an automated cryogenic wafer prober to pre-train a 3-hidden-layer neural network (NN) model. Transfer learning based on the NN model was then conducted using another small dataset from 2 bulk MOSFETs. The transfer learning NN model predicted more realistic I-V characteristics and threshold voltages than a control NN model trained using only the small dataset. This study demonstrates cryogenic MOSFET characteristics prediction from a small dataset to reduce time and financial costs for developing cryo-CMOS devices.

Characterization and De-Embedding of Wafer Probe Radiation for Integrated Antenna Measurements

Characterization and De-Embedding of Wafer Probe Radiation for Integrated Antenna Measurements

An improved crack probability model for silicon oxide layers using three-parameter Weibull analysis

For semiconductor dielectric layer crack detection in real-time we developed an efficient and very accurate method, which is based on acoustic emission (AE) testing and simulates the wafer probing process. The crack probability is determined using clustered and filtered AE data, that is collected by an advanced sensor-indenter system. The derived distribution function is based on two-parameter Weibull analysis, which is commonly applied for stress-induced failures of brittle materials like silicon oxide (SiO2). During indenter experiments, we observed, that the probability model for a higher number of data points is becoming inaccurate, especially at low fracture forces. Therefore, we introduce a more accurate statistical model for probing-induced SiO2 layer cracks, which is, according to a three-parameter Weibull distribution, considering a location parameter. Experimental results have shown, that the improved distribution function fits much better for predicting low-ppm failure rates of back-end-of-line (BEOL) stacks of CMOS technologies. This enables more reliable pad stack design rules and increases the reliability of complex chip designs regarding mechanical stress during test and assembly processes.

Modeling of the impact of mechanical stress resulted from wafer probing and wire bonding on circuit under pad

Circuit Under Pad (CUP), also known as Bond Pad Over Active (BPOA), has been gaining popularity in the semiconductor industry. However, such a design concept amplifies the effect of stress-inducing processes, which are detrimental to the chip's electrical performance and mechanical reliability. The said processes are wire bonding and wafer probing, and they are unavoidable in the manufacturing of a semiconductor. Although the Finite Element Analysis (FEA) of these processes has been carried out in previous research, the focus was not on the polysilicon resistor or metallization layers in CUP, but on the bond pad only. On the other hand, wire bonding is carried out after wafer probing in the manufacturing line. However previous studies, either numerically or experimentally, investigated the processes separately. Specifically, those studies did not link the stress and deformation history of the wafer-CUP structure resulting from the wafer probing to the stress and deformation induced in the subsequent wire bonding process. Therefore, this project scoped both simulations in a continuous manner and using a CUP design as the chip's structure. ANSYS Mechanical was utilized to simulate the dynamic wafer probing and thermosonic wire bonding. The result showed that copper bonding exerted more stress compared to gold bonding. Meanwhile, the Cu/low-k chip is more sensitive to stress-inducing factors than the Al/SiO2 chip.

A 17.7–19.2-GHz Receiver Front End With an Adaptive Analog Temperature- Compensation Scheme

This article presents an eight-element 17.7–19.2-GHz receiver front end with 1–2 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes a temperature-compensation variable-gain amplifier (TC-VGA) to minimize the temperature-induced gain variation. The concept of the proposed TC-VGA and the realization of corresponding adaptive analog control are introduced in detail. The front-end architecture and circuit-level design to enable a flat wideband gain response, precise phase and amplitude control, low power consumption, and adaptive analog temperature compensation are presented. Wafer probing is conducted to measure the performance of the receiver front end. The measured gain-temperature coefficient is ±0.005 dB/°C from −15°C to 85 °C at 17.7–19.2 GHz, while the counterpart without temperature compensation is −0.1 dB/°C. The chip demonstrates a 28-dB power gain, a 26% 3-dB fractional bandwidth, a 3.2–4.1-dB noise figure (NF), and a −27.4-dBm input 1-dB gain compression point (IP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) for each element. In addition, each channel provides 7-bit phase-shifting resolution and 6-bit attenuation for a 15.75-dB gain range with a <1.5° root-mean-square (rms) phase error, and a < 0.22-dB rms amplitude error. The chip occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.65\times2.77$ </tex-math></inline-formula> mm2 area with pads, equivalent to 1.61 mm2 per element (for two beams), and consumes 37.2 mW per element per beam. To the best of our knowledge, the receiver front end demonstrates the minimum gain variation with temperature among silicon RF-beamforming front ends.

Path Planning of Randomly Scattering Waypoints for Wafer Probing Based on Deep Attention Mechanism

Wafer probing is a critical process employed to measure the yield of wafer fabrication. The primary object of wafer probing is to find the defect grain on the wafer. After a full coverage check, there are always some suspected grains existing for further inspection. However, this second probing result could be affected by the shape of the probe card and the setting actions (path planning) of operators for grains randomly scattering on the wafer. Good grains can be damaged by reprobe actions, which decrease production performance and customer trust. In general, it also requires manpower to perform reprobing, which dramatically deteriorates the throughput of production. This article has studied this problem, and an adaptive coverage path planning (CPP) method for randomly scattering grains using an attention interface is proposed. The proposed randomly scattering waypoints method uses deep reinforcement learning (DRL) for automatic real-time path planning of the second detection. A soft attention interface accelerates the process with a less overlapped check. The experimental results demonstrate the efficiency of the proposed method in terms of less overlapping and steps, and this method learns a better CPP strategy for wafer probing than programmed paths and other RL-based methods.

Advances in machine learning for large-scale manufacturing of photonic circuits

Machine learning has opened a new realm of possibilities in photonic circuit design and manufacturing. First, we describe our approach of using deep learning to optimize the multi-dimensional parameter space for hundreds of optical chips on a mask, resulting in homogeneity of performance in high volume applications. Second, we present our approach of using a support vector machine to predict the performance of optical devices by wafer probing. This approach eliminates the expensive and labour-intensive process of optical chip testing, and allows unprecedented control over the fabrication process, including in-situ monitoring of wafer fabrication and real-time process adjustments. The combination of these two approaches paves the way for accelerated adoption of photonics in high volume applications.

Nanoindentation characterization of thin film stack structures by finite element analysis and experiments using acoustic emission testing

Increased risk of crack formation in the brittle insulating layers of crack-sensitive backend-of-line (BEOL) structures in semiconductor integrated circuits during wafer probing or wire bonding process is detrimental to product reliability. This paper describes the use of a high-resolution, in-situ material testing system that integrates acoustic emission (AE) testing with a nanoindentation system, as well as the finite element analysis (FEA) simulation method, for faster characterization of BEOL structures to optimize the reliability of wafer probing and wire bonding processes. This hybrid testing system is used to determine the critical load of thin film stack structures with Al-Cu input/output (I/O) pads, insulating layers, and the embedded Cu layers. Cracks were induced during the nanoindentation, and scanning electron microscopy (SEM) confirmed the formation and propagation of cracks in the insulating layers below the I/O pad. Finite element analysis (FEA) simulation was carried out to evaluate the contact-related stress distribution and obtain the critical stress by replicating the nanoindentation process to fully understand the critical conditions that lead to brittle fracture in insulating layers. Multiple thin film stack structures with different layer thicknesses are tested by experiment and correlated with simulation in parameter studies. We observed that as the thickness of the insulating layer increases and as the thickness of the embedded copper layer decreases, the critical loads will increase, which is in good agreement with previous studies. We also discovered that the critical loads of structures with thicker metal pads are not always higher than the thinner ones, which means the thicker metal pads do not certainly protect the structures better, as previous studies discovered.

Focus on software, data acquisition, and instrumentation

Focus on software, data acquisition, and instrumentation

Long Stroke Design of Piezoelectric Walking Actuator for Wafer Probe Station.

In order to develop a high-resolution piezoelectric walking actuator with a long stroke for the wafer probe station, this work presents a design of a piezoelectric walking actuator with two auxiliary clamping feet elastically attached to major clamping feet. Its construction was introduced and its operating principle was analyzed. Structure design details were discussed and a prototype was proposed. The prototype was fabricated and tested. The experimental results show that the proposed actuator can operate stably along a 20 mm guider. The proposed design is suitable for precision motion control applications.

Stabilizing amplifier with a programmable load line for characterization of nanodevices with negative differential resistance.

Resistive switching devices and other components with negative differential resistance (NDR) are emerging as possible electronic constituents of next-generation computing architectures. Due to the exhibited NDR effects, switching operations are strongly affected by the presence of resistance in series with the memory cell. Experimental measurements useful in the development of these devices use a deliberate addition of series resistance, which can be done either by integrating resistors on-chip or by connecting external components to the wafer probing system. The former approach is considered inflexible because the resistance value attached to a given device cannot be changed or removed, while the latter approach tends to create parasitic effects that impact controllability and interfere with measurements. In this work, we introduce a circuit design for flexible characterization of two-terminal nanodevices that provides a programmatically adjustable external series resistance while maintaining low parasitic capacitance. Experimental demonstrations show the impact of the series resistance on NDR and resistive switching measurements.

Analog Frontend for Reliable Human Body Temperature Measurement for IoT Devices

In this paper an analog frontend for a reliable measurement of the human body temperature is presented. A new and novel temperature calibration technique using an on-chip resistor was developed specifically for the analog frontend. The discussed analog frontend consists of a bandgap current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and an on-chip calibration resistor. The developed calibration technique enables very high accuracy, even 0.1 °C, to be obtained in a very wide temperature range. This calibration method was elaborated for integrated circuits operating in temperatures from −40 °C to +125 °C. The presented analog frontend consumes no more than 185 μA and was designed and manufactured with United Microelectronics Corporation (UMC) CMOS 130 nm technology. The data presented in the paper were obtained from process corner and Monte Carlo simulations as well as from measurements. The measurements were taken using a manual wafer prober with climate-controlled microchamber, at temperatures ranging from −40 °C to +125 °C.

A comparison of pad metallization in miniaturized microfabricated silicon microcantilever-based wafer probes for low contact force low skate on-wafer measurements

Miniaturized, microfabricated microelectromechanical systems-based wafer probes are used here to evaluate different contact pad metallization at low tip forces (<mN) and low skate on the on-wafer pads. The target application is low force RF probes for on-wafer measurements which cause minimal damage to both probes and pads. Low force enables the use of softer, more conductive metallisation. We have studied four different thin film contact pad metals based on their thin film electrical resistivity and micro-hardness: gold, nickel, molybdenum, and chromium. The contact pads sizes were micrometre (1.9 × 1.9 µm2) and sub-micrometre (0.6 × 0.6 µm2). The contact resistance of Au–Au, Ni–Au, Mo–Au, and Cr–Au was measured as a function of tip deflection. The tip force (loading) of the contacts was evaluated from the deflection of the cantilever. It was observed that an overtravel of 300 nm resulting in a contact force of ∼400 µN was sufficient to achieve a contact resistance <1 Ω for a sub-micrometre gold contact pad. Our results are compared with an analytical model of contact resistance in loaded metal-metal contacts—a reasonable fit was found. A larger contact resistance was observed for the other metals—but their hardness may be advantageous when probing other materials. Using a combination of a rigid silicon cantilever (>1000 Nm−1) and small contact pads enabled us to show that it is the length of the pad (in contact with the surface) which determines the contact resistivity rather than the total contact pad area.

FinFET Response under Radiation and Bias Stress

Abstract: The study of FinFET Response under various parameters change is widely studied in many branches of Electronics Engineering. FinFET structure is going beyond the downscaling limit of the conventional planar CMOS technology. The major applications of FinFET have been mainly devoted to digital circuits, analog circuits, and targeting a successful mixed integration of analog and digital circuits. The purpose of this paper is to provide a clear and exhaustive understanding of the state of the art, challenges, and future trends of the FinFET technology from a microwave modeling perspective. Inspired by the traditional modeling techniques for conventional MOSFETs, different strategies have been proposed over the last years to model the FinFET behavior at gamma radiation. With the aim to support the development of this technology, a comparative study of the achieved results is carried out to gain both useful feedbacks to investigate the microwave FinFET performance as well as valuable modeling. Keywords: CMOS, MOSFET, FinFET, Hot carriers, Gamma Chamber, SCE, DIBL, Oslo Si-Bulk FinFET, Wafer probe station.

Cluster-based acoustic emission signal processing and loading rate effects study of nanoindentation on thin film stack structures

This paper presents a high-resolution, in-situ material testing system that integrates acoustic emission (AE) testing with a nanoindentation system for crack generation and detection in thin film stack structures. This is used to find the critical contact load during wafer probing of crack-sensitive backend-of-line (BEOL) structures in semiconductor integrated circuits. Scanning electron microscopy (SEM) and load–displacement curve analysis were used to confirm the formation and propagation of cracks in the multilayer structures. In order to improve the manual classification performance and understand the physical meaning of AE signals, this paper introduces a machine learning based signal processing approach based on a k-means clustering algorithm applied on collected AE signals. To obtain the optimal number of k-means clusters, Davies–Bouldin, Dunn, and Silhouette indices were calculated, and the individual ratings were cumulated based on a voting scheme. Multiple feature extraction methods, including raw time-domain AE signals, conventional AE extracted parameters, short-term signal energy, and representation features learned by the autoencoder, were used and evaluated by manually labeled clusters and binary confusion matrices. A supervised learning technique, the k-nearest neighbors algorithm, was also utilized on different AE signal datasets using different loading rates to further investigate the damage processes during nanoindentation and the physical meaning of different AE signals. The influences of loading rates on AE signals have been investigated, and loading rate effects on the critical load were observed – higher loading rates led to higher critical loads. This integrated test system and signal processing approach provides a high-resolution mechanical testing platform for studying and enabling automatic crack detection in wafer probing.

Self-regulated parallel process 3-D array microfabrication with metal direct-write

Parallel process direct-write manufacturing of ultrahigh aspect ratio 3-D metal microstructures remains one of the ultimate challenges in 3-D manufacturing. Its development promises novel solutions for high density chip scale packaging and sorting that require precision microscale mechanical and electrical interfaces to microelectronics. Herein, we exploited a self-regulated growth mechanism revealed in the meniscus-confined direct-write electro-deposition to realize the parallel process fabrication of high-density area arrays of ultrahigh aspect-ratio metal microwire structures. We demonstrated the direct-write fabrication of an array of curvilinear metal spirals over 800 μm in height and 50 μm in array spacing, structurally and mechanically appropriate for high density wafer probe testing applications that cannot otherwise be fabricated with any other existing methods.