Wafer-level Hermetic Packaging Research Articles

Failure analysis of fabrication process in hermetic wafer-level packaging for microbolometer focal plane arrays

Wafer-level hermetic packaging is attractive for microbolometer-based uncooled infrared cameras as it enables low manufacturing cost and high-volume production of the sensors. A large package is designed to accommodate highly sensitive microbolometers with a high pixel count. This paper focuses on the study of failure mechanisms related to fabricating such large hermetic packages at wafer-level. We bonded wafers containing ~12 mm × 12 mm dies using CuSn solid-liquid interdiffusion (SLID) bonding and subsequently analysed the possible causes for failures. A time-dependent cap deflection study was carried out on the successfully bonded dies to evaluate the vacuum condition inside the package. The main causes for failures determined by this study include insufficient bonding pressure, non-uniform electroplating, voids in the sealing frame, and local cracks on the cap wafer with cavity. These factors contribute to a low dicing yield and loss of vacuum. A high dicing yield were obtained by Cu electroplating with 5 mA/cm2 current density, ≥4 MPa bonding pressure, and ≥200 μm cap thickness. In the cap deflection study, 7 out of 19 dies in a wafer maintained high vacuum after 178 days as indicated by limited decline in the cap deflection (~1–6 %), which shows the potential of this wafer-level packaging for obtaining long-term reliability.

Development of Low Temperature Double Level TSV, Hole and Seal Process for Low Pressure Zero Level MEMS Packaging

Through Silicon Via (TSV) technology is considered one of the key methods to enable heterogeneous integration at the third dimension and realize electrical interconnection between device parts. In that context, different components (MEMS, sensors, circuits etc.) can be electrically integrated in 3D manner, increasing stack density, shrinking footprint, and reducing fabrication costs. At MEMS integration, it is important to explore the packaging method that enables the optimum performance of the active MEMS component and the TSV approach to electrically connect it with the package. Herein, we present our via-last approach to integrate a zero-level packaged MEMS wafer defined by cavity SOI (C-SOI) and CMOS readout circuitry (at thermal budget <400ºC). TSV distribution and fabrication route ensures the electrical connectivity of MEMS inertial sensor and CMOS. Furthermore, a hole is added to the layout scheme and sealed afterwards to ensure low pressure encapsulation in the MEMS cavity.In our previous work related to MEMS fabrication [1], we elaborated the superiority of C-SOI start material over conventional fabrication methods (like vapor HF). In our approach, MEMS cavity structures are realized by patterning dielectrics and the moving parts by employing deep Si etch (DSiE) method (Fig 1 a-c). To enhance the dielectric surface smoothness prior bonding, a complementary HF -based clean applied. This way, bonding requirements (Rq<1nm, Rrange<10nm) are met. CMOS wafer is fabricated with a single layer of Cu damascene process in a dielectric stack to create complementary bonding medium for MEMS wafer. Selected dielectrics at MEMS (thermal oxide) and CMOS (SiCN) can perform better at low temperature fusion bonding due to their moisture blocking capability. Next, fusion bonding at room temperature is carried out using assisted force (60kN) to enhance bonding efficiency and completed by curing the wafer pair at 350˚C.In this paper, we present further work to complete the MEMS zero-level packaging through electrical connections and vacuum seal. Fabrication sequence continues on the backside of the MEMS wafer (Fig 1d-g). First the desired top membrane (cap) thickness of MEMS wafer realized by thinning bulk Si substrate down to 50µm. After SiOx deposition, a double TSV approach is carried out aiming to create the electrical interconnections between the package components, one to reach to the sensor parts in MEMS wafer and one to reach to CMOS. TSV for enabling the connection with sensor parts (12x50μm) is realized by DSiE through the top Si membrane and buried oxide (BOX) landing at Si epi layer of C-SOI. Isolation of this TSV is obtained by conformal liner deposition using SACVD SiOx (350C). Liner opening at the TSV base is assisted by a second non-conformal dielectric deposition to protect the sidewall isolation during resistless directional liner etch back at TSV bottom. Metallization of the via is carried out by sequential PVD barrier (Ta) and seed (Cu) depositions; and the TSV is filled with electroplated Cu. MEMS top surface is then cleared either by CMP or by wet and dry etching of Cu and Ta, respectively. TSV for connecting to CMOS (20x80μm) follows the same processing route with an additional DSiE through all the C-SOI MEMS stack and landing on designated plugs on CMOS. With these two TSV schemes it is ensured to bias and measure the inertial sensor, its driving circuitry, and the zero-level package (Fig. 2a)Once the two TSVs fabrication is completed, hole for the vacuum sealing can be created. First, the top dielectric on surface of MEMS wafer is etched in circular areas of diameter 10μm to define where the venting holes will be created. This is mainly to expose Si surface and reduce possible leakage paths, as well as to increase the adhesion of the deposited metallization to close the hole under vacuum. Small hole (Ø2μm) is defined in the middle of the Si circular area by lithography and etching through the top MEMS membrane (50μm) landing on the cavity of the C-SOI (Fig 1f). Vacuum seal of the zero-level package is finalized with bond pad creation which also seals the hole under vacuum. Al deposition is carried out at high vacuum PVD system; the hole is simultaneously sealed and preserve the same vacuum as the PVD chamber. Along with the chamber vacuum level, the Al thickness and power is also very important to achieve the desired seal Fig.2b.Proposed work enables zero-level MEMS hermetic packaging with integrated CMOS and developed on 200mm wafers.[1] Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging, A.Malainou, J.Visker, D.Sabuncuoglu, 21st EPTC, Singapore 2019 Figure 1

Development of 3D Wafer Level Hermetic Packaging with Through Glass Vias (TGVs) and Transient Liquid Phase Bonding Technology for RF Filter.

The development of 5G mobile communication created the need for high-frequency communication systems, which require vast quantities of radio frequency (RF) filters with a high-quality factor (Q) and low inband losses. In this study, the packaging of an RF filter with a through-glass via (TGV) interposer was designed and fabricated using a three-dimensional wafer-level package (3D WLP). TGV fabrication is a high-yielding process, which can produce high precision vias without masking and lithography and reduce the manufacturing cost compared with the through silicon via (TSV) solution. The glass interposer capping wafer contains Cu-filled TGV, a metal redistribution layer (RDL), and the bonding layer. The RF filter substrate with Au bump is bonded to the capping wafer based on Au-Sn transient liquid phase (TLP) bonding at 280 °C with a 40 kN (approximately 6.5 MPa) bonding force. Experimental results show that shear strengths of approx. 54.5 MPa can be obtained, higher than the standard requirement (~6 MPa). In addition, a comparison of the electrical performance of the RF filter package after the pre-conditional level three (Pre-Con L3) and unbiased highly accelerated stress (uHAST) tests showed no difference in insertion attenuation across the passband (<0.2 dB, standard value: <1 dB). The final packages passed the reliability tests in the field of consumer electronics. The proposed RF filter WLP achieves high performance, low cost, and superior reliability.

Effect of Au Film Thickness and Surface Roughness on Room-Temperature Wafer Bonding and Wafer-Scale Vacuum Sealing by Au-Au Surface Activated Bonding.

Au-Au surface activated bonding (SAB) using ultrathin Au films is effective for room-temperature pressureless wafer bonding. This paper reports the effect of the film thickness (15–500 nm) and surface roughness (0.3–1.6 nm) on room-temperature pressureless wafer bonding and sealing. The root-mean-square surface roughness and grain size of sputtered Au thin films on Si and glass wafers increased with the film thickness. The bonded area was more than 85% of the total wafer area when the film thickness was 100 nm or less and decreased as the thickness increased. Room-temperature wafer-scale vacuum sealing was achieved when Au thin films with a thickness of 50 nm or less were used. These results suggest that Au-Au SAB using ultrathin Au films is useful in achieving room-temperature wafer-level hermetic and vacuum packaging of microelectromechanical systems and optoelectronic devices.

Hermetic Sealant Material Possibilities for IR Sensor Packaging

Hermeticity is one of the most critical issues for infrared (IR) sensor packages, since any leakage will impair the functionality of the device. The issues associated with the premature failure of hermetic sealants were studied in detail, both by simulation as well as by experimentation. Alternate prospective hermetic sealant candidates for transistor outline IR sensor packages were identified and evaluated. Hermetic sealant options for wafer-level IR sensor packaging were also investigated, which involves wafer-level hermetic cum vacuum packaging. Metallic hermetic sealant is preferred for this approach, since it facilitates integration with the getter material. However, the primary challenge encountered here is the requirement of high processing temperature for the getter activation. An activated getter adsorbs active gases inside the volume of the packages, resulting in lower internal pressure. It was determined that appropriate micro-alloying of the getter is required to minimize the getter activation temperature. This is achieved by selective micro-alloying of the getter material, which induces more grain boundaries and thereby promotes in-depth diffusion even at lower activation temperature. Integration of getter material with all three different types of metallic wafer-level bonding mechanisms was investigated. This includes eutectic, diffusion and transient liquid-phase bonding mechanisms. Selection of an appropriate bonding mechanism and integration scheme depends on the corresponding structure, layout and temperature rating of the specific IR sensor devices.

(Invited) Hermetic Wafer-Level Packaging of Microbolometers for Uncooled Thermal Cameras

Infrared (IR) and thermal imaging industry has been increasingly expanding outside of its traditional military scope to cover a variety of consumer products, surveillance, and security applications. The market for thermal imaging is expected to double in the next 5 years and reach an amount of $8 billion by 2021. This increasing demand for thermal imaging technology is expected to reduce the unit price per device, which puts pressure on the industry to lower production costs. For low-cost consumer products, thermal imaging is based on microbolometer technology which does not require cooling, works in short-range, and provides live-video feed of surroundings. Microbolometers comprise of IR sensitive material that undergoes a change in electrical resistance upon absorbing IR radiation. In order to minimize losses, improve the resolution of the thermal imager, and extend its lifetime, the material is thermally isolated from its surrounding environment by enclosing it in a low vacuum micro-cavity. The micro-cavity is formed by bonding a cap wafer to the device wafer, which allows encapsulating tens of devices at the same time. This form of bonding, known as wafer-level packaging, significantly cuts the microbolometer production cost. When used for consumer products, the thermal imaging device must operate for 5-10 years, depending on the targeted application, before its performance deteriorates. To prolong the lifetime of the device, the vacuum in micro-cavities must be sustained. Several steps must be implemented in order to achieve and maintain proper operation conditions: i) a hermetic sealing of the cavity should be realized to minimize gas leakage from surrounding environment; ii) degassing of the system before seal-off is needed to dislodge and release trapped gases within the materials; and if necessary, iii) incorporating a non-evaporable getter which acts as a chemical pump to rid the system of residual gases during the device lifetime. In this presentation, we provide an overview of current challenges in hermetic wafer-level packaging of microbolometers, which is a crucial step in the large scale production of uncooled thermal cameras. The presentation will address advantages and limitations of different bonding processes. Special focus will be made on fluxless AuSn solder and its use to achieve hermetic wafer-level packaging. Results of temperature-dependent surface analysis studies including in situ and ex situ spectroscopic and microscopic techniques (LEEM/PEEM, XPS, SEM-NanoAuger, and TEM) will be discussed to highlight key mechanisms in wafer preprocessing (e.g. patterning of the seal rings) and establish key parameters controlling the quality of the bonding. The role of pre-processing at elevated temperatures in degassing the cavity from non-getterable gases and its influence on Sn and Ti surface diffusion will be discussed. This surface diffusion yields to the formation surface oxide, which is detrimental to the bonding process.

Low-temperature hermetic thermo-compression bonding using electroplated copper sealing frame planarized by fly-cutting for wafer-level MEMS packaging

Hermetic packaging plays an important role for optimizing the functionality and reliability of a wide variety of micro-electro-mechanical systems (MEMS). In this paper, we propose a low-temperature wafer-level hermetic packaging method based on the thermo-compression bonding process using an electroplated Cu sealing frame planarized by a single-point diamond mechanical fly-cutting. This technology has an inherent possibility of hermetic sealing and electrical contact as well as a capability of integration of micro-structured wafers. Hermetic sealing can be realized with the sealing frame as narrow as 30 μm at a temperature as low as 250 °C. At such a low bonding temperature, a less amount of gases is desorbed, resulting in a sealed cavity pressure lower than 100 Pa. The leak rate into the packages is estimated by a long-term sealed cavity pressure measurement for 7 months to be less than 1.67 × 10−15 Pa m3 s−1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

Comprehensive Die Shear Test of Silicon Packages Bonded by Thermocompression of Al Layers with Thin Sn Capping or Insertions.

Thermocompression bonding for wafer-level hermetic packaging was demonstrated at the lowest temperature of 370 to 390 °C ever reported using Al films with thin Sn capping or insertions as bonding layer. For shrinking the chip size of MEMS (micro electro mechanical systems), a smaller size of wafer-level packaging and MEMS–ASIC (application specific integrated circuit) integration are of great importance. Metal-based bonding under the temperature of CMOS (complementary metal-oxide-semiconductor) backend process is a key technology, and Al is one of the best candidates for bonding metal in terms of CMOS compatibility. In this study, after the thermocompression bonding of two substrates, the shear fracture strength of dies was measured by a bonding tester, and the shear-fractured surfaces were observed by SEM (scanning electron microscope), EDX (energy dispersive X-ray spectrometry), and a surface profiler to clarify where the shear fracture took place. We confirmed two kinds of fracture mode. One mode is Si bulk fracture mode, where the die shear strength is 41.6 to 209 MPa, proportionally depending on the area of Si fracture. The other mode is bonding interface fracture mode, where the die shear strength is 32.8 to 97.4 MPa. Regardless of the fracture modes, the minimum die shear strength is practical for wafer-level MEMS packaging.

Wafer-level hermetic vacuum packaging by bonding with a copper–tin thin film sealing ring

A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper–tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67 × 10−17 Pa · m3 s−1, corresponding to an air leak rate of 6.19 × 10−18 Pa · m3 s−1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

Wafer-Level Hermetic Package by Low-Temperature Cu/Sn TLP Bonding with Optimized Sn Thickness

In this paper, a wafer-level package with hermetic sealing by low-temperature Cu/Sn transient liquid phase (TLP) bonding for a micro-electromechanical system was introduced. A Cu bump with a Sn cap and sealing ring were fabricated simultaneously by electroplating. The model of Cu/Sn TLP bonding was established and the thicknesses of Cu and Sn were optimized after a series of bonding experiments. Cu/Sn wafer-level bonding was undertaken at 260°C for 30 min under a vacuum condition. An average shear strength of 50.36 MPa and a fine leak rate of 1.9 × 10−8 atm cc/s were achieved. Scanning electron microscope photos of the Cu/Sn/Cu interlayers were presented, and energy dispersive x-ray analysis was conducted simultaneously. The results showed that the Sn was completely consumed to form the stable intermetallic compound Cu3Sn. An aging test of 200 h at 200°C was conducted to test the performance of the hermetic sealing, while the results of shear strength, fine leak rate and bonding interface were also set out.

Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than Pa m3s−1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au–Si eutectic bonding techniques. The dies sealed with anodic and Au–Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au–Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au–Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

Wafer-Level Hermetic All-Glass Packaging for Microalkali Vapor Cells of Chip-Scale Atomic Devices

To maintain a controllable environment for microalkali vapor cells of high-performance chip-scale atomic devices, a novel wafer-level hermetic all-glass packaging technology for microalkali vapor cells of atomic devices was investigated. A glass wafer with metal vias was used as the substrate to host the miroalkali vapor cells. Wafer-level hemispherical glass bubbles prepared by a chemical foaming process were used as transparent packaging caps. The performance of the rubidium vapor cell in the all-glass hermetic package was characterized by a laser frequency locking system and an ultraviolet spectrophotometer. The results show that hermetic all-glass packaging at a wafer level was demonstrated successfully. The results also indicate that after the hermetic all-glass packaging, the temperature variation of the microalkali vapor cells was controllably below 0.2 °C at different working temperatures of atomic devices. A chip-scale atomic magnetometer using the hermetic all-glass micro vapor cell was demonstrated eventually.

Interfacial reactions and diffusion path in gold–tin–nickel system during eutectic or thermo-compression bonding for 200 mm MEMS wafer level hermetic packaging

In this work, Au–Sn eutectic bonding and Au–Sn thermo-compression bonding are studied for applications in hermetic packaging at wafer level. Eutectic bonding experiments were performed under vacuum or pure nitrogen at temperatures between 310 and 400 °C while thermo-compression bonding experiments were performed under vacuum at 270 °C. Nickel layers 350 nm thick are used as wetting layers on both cap and device sides. During these experiments, the interaction of electrodeposited Au–Sn alloy with nickel layers is studied either in solid or liquid state. The diffusion paths at 270 °C as well as during isothermal solidification of the joint at 310, 350 and 400 °C are determined in relation with the thicknesses of the reaction layers formed at the interfaces and the microstructure of the joint. The effective interdiffusion coefficient in the ζ-Au5Sn phase is deduced at 270 and 310 °C. Moreover, the melting and solidification process of electrodeposited Au/Sn layers with an overall eutectic composition were studied by Differential Scanning Calorimetry in a specific configuration that does not involve the interaction of Au–Sn alloy with the nickel layer. Bonded wafers with good mechanical properties were characterized by cross-section Scanning Electron Microscopy using Energy Dispersive X-ray mode. The mechanical strength of the seal was checked by blade plate insertion technique.

Wafer level hermetic sealing of MEMS devices with vertical feedthroughs using anodic bonding

This paper presents a new method for wafer-level hermetic packaging of MEMS devices using a relatively low temperature anodic bonding technique applied to the recently developed advanced MEMS (aMEMS) process. The aMEMS process uses vertical feedthroughs formed on an SOI cap wafer, eliminating the need for any complex via-refill or trench-refill steps while forming the vertical feedthroughs. The hermetic sealing process is achieved at 350°C by using an anodic bonding potential of 600V. The bonding process does not require any sealing material on neither the cap nor the sensor wafer. The packaging yield is experimentally verified to be 94% for 4 wafers packaged up to date, and the cavity pressure is measured to be as low as 1mTorr with successfully activated Titanium thin film getter. The cavity pressure can be set to different levels ranging from 1mTorr up to 5Torr, simply by varying the outgassing period and utilization of the getter material, enabling the proposed method be used for various types of MEMS devices with different pressure requirements. The pressure inside the encapsulated cavities has been monitored for 6 months since the first prototypes, and it is observed that pressure is stable below 5mTorr throughout this period. The shear strength of 6 packages is measured to be above 10MPa, whereas the shear failure occurs not at the bonding interface but the vertical feedthroughs, which have lower strength compared to the bonding region. The robustness of the packages is tested by subjecting them to cyclic thermal tests between 100°C and 25°C, and no degradation is observed in the hermeticity of the packages at the end of this period. The vacuum level of the packages is also verified to be unchanged by storing the packages at 150°C for 24h. Moreover, it is experimentally verified that the hermeticity of the packaged chips can withstand ultra-high temperature shocks as high as 400°C for 5min.

Wafer-level Au–Au bonding in the 350–450 °C temperature range

Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au–Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au–Si eutectic temperature 363 °C is recommended.

A Wafer-Level Sn-Rich Au—Sn Bonding Technique and Its Application in Surface Plasmon Resonance Sensors

Sn-rich Au—Sn solder bonding is systematically investigated. High shear strength (64MPa) and good hermeticity (a leak rate lower than 1 × 10−7 torr·l/s) are obtained for Au—Sn solder with 54 wt% Sn bonded at 310°C. The AuSn2 phase with the highest Vickers-hardness among the four stable intermetallic compounds of the Au—Sn system makes a major contribution to the high bonding strength. This bonding technique has been successfully used to package the Surface Plasmon Resonance (SPR) sensors. The Sn-rich Au—Sn solder bonding provides a reliable, low-cost, low-temperature and wafer-level hermetic packaging solution for the micro-electromechanical system devices and has potential applications in high-end biomedical sensors.

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O2 generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.

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用电镀铜锡合金薄膜实现圆片级气密封装

Resonant biaxial 7-mm MEMS mirror for omnidirectional scanning

Low-cost automotive laser scanners for environmental perception are needed to enable the integration of advanced driver assistant systems into all automotive vehicle segments, which is a key to reduce the number of traffic accidents on roads. Within the scope of the European-funded project MiniFaros, partners from five different countries have been cooperating in developing a small-sized low-cost time-of-flight-based range sensor. An omnidirectional 360-deg laser scanning concept has been developed based on the combination of an omnidirectional lens and a biaxial large aperture MEMS mirror. The concept, design, fabrication, and first measurement results of a resonant biaxial 7-mm gimbal-less MEMS mirror that is electrostatically actuated by stacked vertical comb drives is described. Identical resonant frequencies of the two orthogonal axes are necessary to enable the required circle scanning capability. A tripod suspension was chosen, since it minimizes the frequency splitting of the two resonant axes. Low-mirror curvature is achieved by a thickness of the mirror of more than 500 μm. Hermetic wafer-level vacuum packaging of such large mirrors based on multiple wafer bonding has been developed to enable a large mechanical tilt angle of ±6.5 deg in each axis. Due to the large targeted tilt angle of ±15 deg and because of the MEMS mirror actuator having a diameter of 10 mm, a cavity depth of about 1.6 mm has been realized.