Vt Shift Research Articles

Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics

In this study, the authors investigated the addition of zirconium (Zr) into HfO2 to improve its dielectric properties. HfxZr1−xO2 films were deposited by atomic-layer deposition at 200–350°C and annealed in a nitrogen ambient environment at 1000°C. Extensive physical characterization of the impact of alloying Zr into HfO2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. HfxZr1−xO2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO2 leads to changes in film microstructure and grain-size distribution. HfxZr1−xO2 films have smaller and more uniform grain size compared to HfO2 for all deposition temperatures explored here. As Zr content and deposition temperature are increased, stabilization of the tetragonal phase is observed. A monotonic decrease in band gap is observed as ZrO2 content is increased. The chlorine impurity in the films is strongly dependent on deposition temperature and independent of film composition. TEM images of transistors showed excellent thermal stability as revealed by a sharp HfxZr1−xO2∕Si interface and no Zr silicide formation. Significant improvement in device properties such as lower electrical thickness (higher permittivities), lower threshold voltage (Vt) shift after stress (improved reliability), and higher mobilities are observed with Zr addition into HfO2. All of these results show HfxZr1−xO2 to be a promising candidate for SiO2 replacement.

Threshold-Voltage Instability of Single-Crystal Si Thin-Film Transistors Fabricated on Plastic Substrate

Single-crystal Si thin films are transferred onto plastic host substrate after selectively removing the buried oxide (BOX) layer on the silicon-on-insulator (SOI) substrate. A layer of SU-8 epoxy is used as gate dielectric for the thin-film transistors (TFTs) fabricated on the transferred Si thin films. Here we report the first observation of threshold voltage (Vt) instability on these n-type, single-crystal Si TFTs on flexible plastic substrate. It is observed that Vt shifts to higher (lower) value under high positive (negative) gate-bias stressing. The logarithmic time-dependence of the Vt shift suggests that the instability is attributed to charge trapping in the gate dielectric layer.

Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem

The requirements for a high-k metal gate n-mosfet solution are that one has a device that exhibits a low Tinv (<1.5 nm), high mobility (~200 @ 1MV/cm) and a threshold voltage in the range of 0-0.2V. While these properties have been independently demonstrated, the key challenge has been to deliver these properties simultaneously and in a gate first , high temperature process flow. We show, that by introducing a new, ultrathin lanthanum oxide dielectric layer in the gate stack, whose function is to provide an electrostatic shift to the onset of threshold these requirements can be acceptably met. This is carried out without compromising gate capacitance and with minimal degradation to the mobility. The underlying physics behind the threshold shift will also be discussed.

Equivalent Circuit Description of Threshold Voltage Shift in a-Si:H TFTs From a Probabilistic Analysis of Carrier Population Dynamics

Amorphous hydrogenated silicon thin-film transistors (TFTs) are critical components in large area display and sensor systems, and the need for TFT circuits has been increasing. However, the intrinsic metastability associated with the TFT leads to a threshold voltage shift (VT shift) with time, under prolonged gate bias. For design of reliable TFT circuits, it is imperative to accurately predict this instability for time-varying analog gate bias. In this paper, the author model the threshold voltage variation using a probabilistic analysis of the electron population dynamics as prescribed by the defect pool and charge trapping mechanisms. The model is then extended for prediction of the effect of variable gate bias, and in particular the device history, on the VT shift. Based on this model, a passive equivalent circuit is synthesized to accurately predict the VT shift in TFTs for applications in active matrix organic light emitting diode displays and sensors

Stable Organic LED Displays Using RMS Estimation of Threshold Voltage Dispersion

Active matrix organic light-emitting-diode (OLED) displays using the amorphous silicon (a-Si:H) thin-film transistor (TFT) as the active element offer a promising avenue for high-performance displays. However, the TFT is prone to a gate-bias-dependent threshold voltage shift (VT shift) which leads to current instability, thus affecting the pixel brightness. This brief discusses an rms error estimation technique with an HVCMOS-TFT implementation to stabilize the OLED current

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

Linewidth effect and phase control in Ni fully silicided gates

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31 Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth Vt rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 degC, whereas a single-phase Ni31Si12 is obtained over an ~200degC temperature range

Threshold Voltage Control in PMOSFETs with Polysilicon or Fully-Silicided Gates on Hf-Based Gate Dielectric Using Controlled Lateral Oxidation

Large threshold-voltage (Vt) shifts are seen in PMOSFETs with Hf-based highK gate dielectric and polysilicon gates. The polysilicon-highK interface can be modified by introducing a thin interfacial oxide layer using a controlled lateral oxidation (CLO) step after gate patterning. This can reduce the threshold voltage shift to within 0.1V of SiO2 reference for devices with gate length <1mm. The benefit of lower Vt with the lateral oxidation comes at the expense of increased EOT. We therefore tried CLO using fully-silicided NiSi gates since the poly-depletion gain can offset the EOT increase. Our results show that the Vt difference between SiO2 and HfSiO is within 50mV. Moreover, the Ion-Ioff performance shows that while poly gates are lower in performance due to high Vt, the FUSI gates give Ion/Ioff at 1.1V of 180 (μA/μm)/20 (pA/μm) for both Hf- silicates and conventional SiO2. Interfacial modification using CLO can be a potential integration solution for highK gate dielectrics with polysilicon gates.

Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem

not Available.

Label-free electronic detection of biomolecules using a-Si:H field-effect devices

Electrolyte-gate amorphous silicon thin-film transistors (EG-TFT) are used for pH and label-free sensing of biological molecules. In top-gate EG-TFTs, the metal gate is replaced by an electrolyte solution, in which a biasing Pt electrode is immersed. It is possible to switch the TFT on by increasing the voltage of the Pt electrode above a threshold value (VT). EG-TFTs show a decrease in VT when the pH of the electrolyte solution is increased. EG-TFTs also show a shift in VT when exposed to solutions containing molecules of either DNA (VT decreases) or the protein horseradish peroxidase (HRP) (VT increases). Exposure to these solutions results in the adsorption of biomolecules at the dielectric-electrolyte interface which changes the TFT transfer curve and consequently allows electronic label-free detection of the biomolecules.

Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

The effect of negative bias stress on p-FETs is compared for oxide vs. oxynitride gate dielectric, and for (110) vs. (100) surface orientation. Nitrogen causes increased interface state generation near the conduction band edge and reduced defect generation at mid-gap. For oxynitride grown on (110) surface only slight difference is seen compared to (100). The hole trapping contribution to the Vt shift is greater at room temperature compared to 125 °C.

Design of multiplexer in amorphous silicon technology

The large area capability of amorphous silicon technology finds many active matrix displays and imaging arrays employing the a-Si:H thin film transistors (TFTs) as analog switches. The TFTs are limited to simple switching applications due to the low driving current and metastability issues inherent to a-Si:H technology. The most apparent metastability issue in an a-Si:H TFT is threshold voltage (Vt) shift due to prolonged gate bias. The Vt shift is more pronounced for positive gate biases than for negative gate biases. Moreover, in the presence of a pulse gate bias, the Vt shift depends on the frequency of operation. Considering the large number of gate and data lines in displays and imaging arrays, multiplexer circuits can provide benefits such as reducing the pin count of the array, reducing the number of external chips and hence, overall system cost. In amorphous silicon technology, Pass transistor logic (PTL)-based multiplexers (MUXes) are attractive since they can be designed to have manageable Vt shifts and less transistors than logic gates based MUXes. In this article, we present Vt shift measurements on in-house fabricated a-Si:H TFTs under relevant bias conditions and analyze the performance of a PTL-based MUX circuit in a-Si:H technology.

Organic field-effect transistors with polarizable gate insulators

A quasi-stable threshold voltage (Vt) shift is imparted onto field-effect transistors (FETs) with organic semiconductors and polymer dielectrics. Adjustment of Vt from accumulation mode to zero or depletion mode is demonstrated for both p-channel and n-channel FETs, and is accomplished by applying a depletion voltage to the gate prior to device operation. Hydrophobic dielectrics and dopant-resistant semiconductors were advantageous. A pixel circuit that utilizes this nonvolatile memory element is proposed.

Hot-carrier-induced oxide charge trapping and interface trap creation in metal–oxide–semiconductor devices studied by hydrogen/deuterium isotope effect

A method based on the hydrogen/deuterium isotope effect is proposed to separate and quantify the effects of interface trap creation and oxide charge trapping on hot-carrier-induced degradation in n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs). Hydrogenated and deuterated transistors were subjected to hot-carrier stress with a fixed drain voltage Vds and various gate voltages Vgs. The threshold voltage Vt and interface trap density Nit were recorded as a function of stress time. It is found that at low Vgs stress when equal numbers of interface traps are created, the shift of Vt is larger in hydrogenated transistors than in deuterated transistors. Increasing Vgs to 1/3Vds produces no noticeable difference of Vt shift in these two kinds of transistors. However, further increasing Vgs results in larger Vt shift in deuterated transistors than in hydrogenated ones. From a quantitative analysis, the contribution of oxide charge trapping to Vt shift is separated from the contribution of interface trap creation. The results suggest that interface trap creation is the dominant mechanism for hot-carrier-induced degradation in n-channel MOSFETs.

The impact of SILC to data retention in sub-half-micron Embedded EEPROMs

Stress-Induced-Leakage-Current (SILC) in sub-half-micron technology embedded EEPROM has been extensively studied by performing gate stress measurements on pre-conditioned EEPROM arrays. This paper reports that the SILC path is very localized; the SILC path can be turned “on” and “off” statistically independent on the electrical field, as shown by the experiments; the SILC caused Vt shift can be fitted into a power-law against the number of programming/erase cycles; the measured current-voltage characteristics of SILC can be well described with Poole-Frenkel model; and EEPROM retention time prediction can be made by extrapolating the gate stress data with fitted Poole-Frenkel parameters.

Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Abstract Device parameter degradation of p-MOSFETs after N egative B ias T emperature Stress (NBTS) and the related charge trapping mechanisms are investigated in detail. Applying specific annealing experiments to NBT-stressed transistors, the influence of stress-induced oxide charge build-up and interface state generation on the degradation of the electrical parameters is evaluated. It is found, that hole trapping significantly contributes to the NBTS-induced Vt shift. Furthermore, experimental results of the hot-carrier behavior of virgin and NBT-stressed devices demonstrate that only weak correlations between these types of stress and the involved degradation mechanisms exist, which is important in applications with alternating stress situations.

Improved DC Reliability of Polysilicon Thin‐Film Transistors with Deuterium Plasma Treatment

AbstractWe demonstrate the improved reliability of high‐temperature (950°C) processed poly‐Si TFTs passivated in a deuterium plasma ambient. Deuterated TFTs exhibit better resistance to performance degradation under dc stress than hydrogenated TFTs. In particular, VT shift is substantially reduced for deuterated TFTs. Our results indicate that the simple substitution of deuterium gas for hydrogen gas in plasma passivation of poly‐Si TFTs can significantly improve device lifetime.

Changes in regional lung mechanics and ventilation distribution after unilateral pulmonary artery occlusion.

Regional pneumoconstriction induced by alveolar hypocapnia is an important homeostatic mechanism for optimization of ventilation-perfusion matching. We used positron imaging of 13NN-equilibrated lungs to measure the distribution of regional tidal volume (VT), lung volume (VL), and lung impedance (Z) before and after left (L) pulmonary artery occlusion (PAO) in eight anesthetized, open-chest dogs. Measurements were made during eucapnic sinusoidal ventilation at 0.2 Hz with 4-cmH2O positive end expiratory pressure. Right (R) and L lung impedances (ZR and ZL) were determined from carinal pressure and positron imaging of dynamic regional VL. LPAO caused an increase in magnitude of ZL relative to magnitude of ZR, resulting in a shift in VT away from the PAO side, with a L/R magnitude of Z ratio changing from 1.20 +/- 0.07 (mean +/- SE) to 2.79 +/- 0.85 after LPAO (P < 0.05). Although mean L lung VL decreased slightly, the VL normalized parameters specific admittance and specific compliance both significantly decreased with PAO. Lung recoil pressure at 50% total lung capacity also increased after PAO. We conclude that PAO results in an increase in regional lung Z that shifts ventilation away from the affected area at normal breathing frequencies and that this effect is not due to a change in VL but reflects mechanical constriction at the tissue level.

Buried-gate oxide thinning during epitaxial lateral overgrowth for dual-gated metal–oxide–semiconductor field-effect transistors

During epitaxial lateral overgrowth of single‐crystal silicon over thermal SiO2, in the low‐pressure chemical vapor deposition reactor environment, thinning and even pinholes can occur in the underlying gate oxide of in dual‐gated silicon on insulator metal–oxide–semiconductor field‐effect transistors (MOSFETs). The epitaxial lateral overgrowth was grown using dichlorosilane (DCS), HCl, and H2 at 970 °C and 40 Torr. Although the etch rate was very small, the thinning was large enough to change the bottom channel threshold voltage (Vt). Oxide thickness measurements, obtained by ellipsometry and by profilometer measurements, indicated an etch rate of about 0.1 nm/min, which was independently confirmed from MOSFET Vt shift measurements. The oxide etch rate decreased with increasing concentration of HCl and was less for oxides grown from heavily arsenic‐doped than from lightly doped boron silicon.

The evolution of diabetic response to ischemia/reperfusion and preconditioning in isolated working rat hearts

Studies have shown that the diabetic heart exhibits abnormalities in cellular ion transport, which can affect susceptibility to reperfusion-induced ventricular fibrillation (VF), tachycardia (VT) and functional derangements. It has been shown that "preconditioning" renders the heart very resistant to a subsequent prolonged ischemic episode. This phenomenon has been extensively studied in healthy myocardium, but such a study has not been previously done in diseased (hypertrophic or myopathic) hearts. We studied the incidence of reperfusion-induced VF, VT, cardiac function, and ion shifts (Na+, K+, Ca2+, and Mg2+) induced by ischemia/reperfusion in isolated hearts from rats with streptozotocin-induced diabetes. Following 2, 4, 6, and 8 weeks of diabetes, hearts were isolated and subjected to 30 min global ischemia followed by reperfusion. In the 2-week diabetic group the total incidence of VF and VT was reduced from their non-diabetic age-matched control value of 100 and 100% to 42 (P < 0.05) and 42% (P < 0.05), respectively. Such a reduction in the incidence of VF and VT was not observed with progressive diabetes (4, 6, and 8 weeks). In the 2-week diabetics, the reduction in the VF and VT was reflected in the improvement of postischemic function, the reduction of ischemia and reperfusion-induced Na+ and Ca2+ gains, and the prevention in K+ and Mg2+ loss. This diabetes-induced initial protection was not seen in the 4- and 6-week diabetics, and a deterioration of postischemic function was observed in the 8-week diabetics. Four cycles of preconditioning, each consisting of 5 min ischemia followed by 10 min reperfusion, failed to reduce the incidence of VF and VT, improve cardiac function, and prevent ion shifts induced by 30 min ischemia followed by 30 min reperfusion in 4- and 8-week diabetics. In the early phase of diabetes the heart is more resistant to ischemia/reperfusion than the non-diabetic heart. Preconditioning does not afford protection against a prolonged period of ischemia in diabetics, indicating that preconditioning may be a "healthy heart phenomenon".