Vt Degradation Research Articles

Investigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques

Dielectric defects play a crucial role in the reliability of MOSFETs. In this study, we aim to gain a deeper understanding of dielectrics’ degradation by correlating the effective interface (N2D) and bulk (NBT) trap densities extracted by different characterization techniques (I-V, charge pumping, and 1/f noise) under different electrical stress conditions. Additionally, we establish an empirical relation between the increase of NBT (estimated via 1/f noise measurements) and N2D,eff (estimated through the monitoring of threshold voltage shift) after stress. This relation is useful to calculate the expected increase in 1/f noise from the VT degradation models typically made available by the foundries to circuit designers.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

Improvement of cell reliability by floating gate implantation on 1Xnm NAND flash memory

Continuous scaling down NAND flash memory toward below 1Xnm node generation will result in serious floating gate (FG) poly depletion and significantly impact the cell reliability performance. In this study, the FG implantation before inter-poly-dielectric deposition was proposed. We have successfully explored the methods to minimize the FG implanted damage issue and hence the void-free control gate (CG) can be achieved after the CG poly-Si fill-in. After optimizing the FG implanted processes, the cell reliabilities on 1Xnm NAND flash device were verified. The FG poly depletion can be effectively reduced by the additional FG dopant, which results in the significant improvement on the natural threshold-voltage (Vt) distribution width, the program noise, and the program/erase Vt degradation. Moreover, there is no degradation on non-cycle data retention when adding the FG implantation, which suggests no extra FG dopant penetrated into tunnel oxide as the trap sites to enhance the trap-assisted tunneling leakage under high temperature baking.

Effects of Fluorine on the NBTI Reliability and Low-Frequency Noise Characteristics of p-MOSFETs

The concurrent effect of fluorine implantation with various energy and dose on reliability and low-frequency noise characteristics of p-MOSFETs was investigated. The $\Delta $ VT degradation that represents device lifetime of p-MOSFETs with fluorine implantation under negative-bias temperature instability stress was less than that without fluorine implantation. The device lifetimes were improved as the fluorine implantation energy and dose increase. The power law exponent $n $ with the fluorine implantation was larger than that without fluorine implantation. This was related to boron diffusion within the gate oxide because the F atoms enhance the diffusivity of the boron. The difference of flicker noise levels between simulation and measurement data at 1 kHz was much greater than that at 10 Hz, which means that F atoms were mainly located near the Si/SiO2 interface rather than in the bulk oxide. The fluorine implantation reduced the ID-RTS noise amplitude, which was believed to contribute to the effective passivation of the dominant traps within the gate oxide. Also, the flicker noise was less dependent on implantation energy. But, flicker noise was reduced with increasing implantation dose. Therefore, fluorine implantation is potentially significant for reducing low-frequency noise as well as improving reliability characteristics.

Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

With technologies scaling down to 28nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.

Measurement Issues Affecting Threshold-Voltage Instability Characterization of SiC MOSFETs

This work focuses on measurement issues that affect the accuracy of positive bias temperature instability measurements of SiC power MOSFETs using a conventional sweep technique to characterize the threshold voltage, VT. Threshold-voltage shifts occurring during stress are readily recoverable during the measurement, resulting in an underestimation in VT degradation. Recovery of VT due to gate-stress relaxation before or during the measurement was a major source of measurement error that was mitigated by performing an immediate sweep down in gate voltage, VGS, from the stress bias toward threshold. Allowing the gate bias to drop to zero just prior to measuring by sweeping VGS positively resulted in smaller observed degradation due to VT recovery. This result is important, especially in cases where the gate stress has to be completely removed before making any electrical measurements. The VT shift caused by bias stress can quickly recover and yield test results that underestimate the effect of the applied stress. A full recovery of VT was observed following a positive gate bias stress for conditions where the gate was either subject to a negative gate voltage for a few seconds, or when VGS was maintained at zero volts for several minutes.

Direct Experimental Evidence of Hole Trapping in Negative Bias Temperature Instability

Negative bias temperature instability (NBTI) in ultrathin-plasma-nitrided-oxide (PNO) based p-type metal-oxide-semiconductor field effect transistors (pMOSFETs) is investigated at temperatures ranging from 220K to 470K. It is found that the threshold voltage VT degradation below 290 K is dominated by the hole trapping process. Further studies unambiguously show that this process is unnecessarily related to nitrogen but the incorporation of nitrogen in the gate dielectric increases the probability of hole trapping in the NBTI process as it introduces extra trap states located in the upper half of the Si band gap. The possible hole trapping mechanism in NBTI stressed PNO pMOSFETs is suggested by taking account of oxygen and nitrogen related trap centers.

Vitellin- and hemoglobin-digesting enzymes in Rhipicephalus (Boophilus) microplus larvae and females

The aim of the present study was to address the involvement of Rhipicephalus microplus larval cysteine endopeptidase (RmLCE) in protein digestion in R. microplus larvae and adult females. In this work, an improved purification protocol for native RmLCE was developed. Partial amino acid sequence of the purified enzyme indicates that it is the same enzyme as Boophilus microplus cathepsin-L1 (BmCL1). When vitellin (Vt) degradation by egg and larval enzymes was analyzed, stage-specific differences for RmLCE activity in comparison to vitellin-degrading cysteine endopeptidase (VTDCE) were observed. RmLCE is also able to degrade host hemoglobin (Hb). In agreement, an acidic cysteine endopeptidase activity was detected in larval gut. It was shown that cysteine and aspartic endopeptidases are involved in Vt and Hb digestion in R. microplus larvae and females. Interestingly, we observed that the aspartic endopeptidase Boophilus yolk cathepsin (BYC) is associated with a cysteine endopeptidase activity, in larvae. Synergic hemoglobin digestion by BYC and RmLCE was observed and indicates the presence of an Hb-degrading enzymatic cascade involving these enzymes. Our results suggest that RmLCE/BmCL1 has a continued role in vitellin and hemoglobin digestion during tick development.

Threshold Voltage and Mobility Extraction by Ultrafast Switching Measurement on NBTI

A simple but robust methodology for the extraction of threshold voltage (Vt) and hole mobility by ultrafast switching measurement on NBTI is demonstrated. It is shown that during the measurement of the linear drain current (Id) versus gate voltage (Vg) curve by ultrafast switching, recovery can be constantly minimized at a very short delay (100 ns) and made independent of the aggregate Id-Vg measurement time (~5 s). In conjunction with the Y -function method, Vt and mobility degradation can be straightforwardly and yet accurately examined over the same measurement voltage range. Moreover, their respective contributions toward p-MOSFET NBTI can clearly be delineated.

A New Fast-Switching NBTI Characterization Method That Determines Subthreshold Slope Degradation

For PMOSFET devices, negative bias temperature instability (NBTI) is a serious reliability concern. Because of recovery effects, careful stress and measurement methods must be used to determine threshold voltage degradation. These methods typically assume that mobility and subthreshold slope (SubSlp) degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses for the first time a unique fast-switching NBTI measurement technique that alternates between two VGS measurement conditions to determine the SubSlp versus stress time. From these measurements, the effect of SubSlp degradation on VT degradation can be accurately determined, and results are compared to the standard techniques.

Interplay between acid phosphatase and cysteine proteases in mediating vitellin degradation during early embryogenesis of Periplaneta americana

In this work, we characterized the activities of two classes of proteases and AcP during early embryogenesis of Periplaneta americana. AcP activity was first detected at day 6 and reached a maximum level at day 10 of development. Using phosphoamino acids, phosphatase activity was shown to be directed only against phosphotyrosine at day 6 while at day 10 it was also active against phosphoserine. In parallel, two classes of proteases were detected and located within yolk granules: a clan CA-cysteine protease, which was inhibited by E-64, insensitive to CA 074 and activated by acidic pH at day 3; and a neutral serine protease, which was inhibited by aprotinin at day 6. Assays of vitellin (Vt) degradation evidenced that incubations at neutral pH induced slight proteolysis, while the incubations at acidic pH did not result in Vt degradation. However, pre-incubations of Vt with AcP increased the levels of Vt acidic proteolysis and this could be inhibited by the addition of phosphatase inhibitors. On the other hand, the same pre-incubations showed no effects on the profile of degradation at neutral pH. We propose that AcP and cysteine protease cooperate to assure Vt breakdown during early embryogenesis of P. americana.