Voltage Transfer Characteristics Research Articles

Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core–shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96 × 10−15 A, −2.33 × 10−5 A, 0.23 × 1010, 42.1 mV V−1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

Photosensitive Complementary Inverters Based on n‐Channel MoS2 and p‐Channel MoTe2 Transistors for Light‐to‐Frequency Conversion Circuits

Photosensitive complementary inverters, composed of multilayered molybdenum disulfide (MoS2) and molybdenum ditelluride (MoTe2), are demonstrated for the applications that require low power consumption and excellent signal‐to‐noise ratio (SNR). The photosensitive characteristics of MoS2, along with the negligible photosensitivity of MoTe2, successfully render them applicable to the light‐to‐frequency conversion circuits that enable high SNR immunity. Under blue light‐emitting diodes (LEDs), the low noise margin and transition width for the voltage transfer characteristics in complementary inverters significantly improve from 1.29 to 1.49 V and 0.24 to 0.31 V, respectively, as compared with those of inverters in the dark. The experimental demonstration of photosensitive inverters and their electrical validations on proposed concepts, supported from SPICE (i.e., simulation program with integrated circuit emphasis) simulation, are systematically obtained, substantiating that this platform can be one of the core parts for future Internet of Things (IOT) applications, which simultaneously demand both ultralow power and robustness on security.

Degradation and Self-recovery of Polycrystalline Silicon TFT CMOS Inverters Under NBTI Stress

Degradation and self-recovery of polycrystalline Silicon (poly-Si) Thin film transistor (TFT) by using complementary metal oxide semiconductor (CMOS) inverter were investigated. Under DC stress, degradation mechanisms were clarified by comparing the Voltage transfer characteristics (VTC) of fresh and stressed inverters. It is determined that Negative bias temperature instability (NBTI) of p-TFT dominates the degradation of the inverter under zero bias DC stress. After removing the stress, the VTC continues to be degraded, because the interface trap-states and the grain boundary trapstates increase due to hydrogen species diffusion. It is found out that the VTC is shifted to its right side severely with negative bias stress of VIN. The NBTI of p-TFT is enhanced and the NBTI of n-TFT also plays a role on the degradation. When removing the negative bias stress, the self-recovery of NBTI of nTFT and the continuing degradation of NBTI of p-TFT become competing mechanisms, together controlling the VTC after-stress behavior. Consequently, the continuing degradation of NBTI of p-TFT is restrained by selfrecovery of NBTI of n-TFT.

A Novel Twofold Tunnel FET With Reduced Miller Capacitance: Proposal and Investigation

A novel twofold tunnel field-effect transistor (TF-TFET) is proposed and investigated for the first time in this paper. The physical characteristics and digital applications of the TF-TFET are demonstrated with rigorous simulation by using Sentaraus TCAD. The proposed TF-TFET is an admixture of both n- and p-type TFETs, and hence, this single device acts as an inverter. It helps to reduce the transistor count in the digital/analog applications. The impact of various device parameters on its performance has been studied extensively. The advantageous factor of the proposed TF-TFET is the presence of an additional capacitance at the drain junction, which helps to reduce the overall Miller capacitance. Moreover, the voltage transfer characteristics (VTC) and transient behavior of the TF-TFET inverter along with some standard cells like XOR gate and 2:1 MUX have been explored using mixed-mode simulation.

Tunnelling-based ternary metal–oxide–semiconductor technology

The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

Influence of AlN etching process on MISFET structures

Purpose The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications. Design/methodology/approach To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO2/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used. Findings In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined. Originality/value The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

An Energy-Band Model for Dual-Gate-Voltage Sweeping in Hydrogenated Amorphous Silicon Thin-Film Transistors

This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current–gate voltage ( ${I}_{\text {D}}$ – ${V}_{\text {G}}$ ) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state $\to $ on-state and the ON-state $\to $ OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the ${I}_{\text {D}}$ – ${V}_{\text {G}}$ curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole–Frenkel region. At the Poole–Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs.

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Oscillators Utilizing Ferroelectric-Based Transistors and Their Coupled Dynamics

We propose the application of ferroelectric (FE)-based transistors, viz., negative capacitance FET (NCFET) and Hysteretic ferroelectric FET (FEFET) in the design of coupled oscillators. The proposed oscillator utilizes hysteretic inverter voltage transfer characteristics, which is achieved by virtue of: 1) negative output conductance (NOC) in NCFETs and 2) hysteretic transfer characteristics in FEFETs. With the aid of output-to-input feedback in the inverter, we show sustained oscillations which are controllable by the gate voltage of the feedback transistor (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BIAS</sub> ). With focus on NCFET-based designs, we show that feedback implementation with pass transistor (PT) and transmission gate (TG) yields relaxation and sinusoid-like characteristics, respectively. Such behavior offers promises for dynamically reconfiguring the oscillator dynamics. We report the fundamental frequency (f) in the range of 12 MHz-800 MHz and 0.7 MHz-417 MHz for TG and PT implementations, respectively. We discuss how this approach can be extended to hysteretic FEFET-based designs. We also analyze coupling between two oscillators considering various strengths of coupling capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> ). We establish the conditions for synchronization of f between the two oscillators with respect to difference in f and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> .

Design of the CMOS inverter‐based amplifier: A quantitative approach

SummaryThe CMOS inverter can be used as an amplifier if properly biased in the transition region of its voltage‐transfer characteristics (VTC). In this paper, the design of this amplifier is investigated with its merits and demerits illustrated and with the various trade‐offs involved in its design discussed. Specifically, the following performance metrics are discussed quantitatively: gain, area, linearity, maximum allowable swing, bandwidth, stability, noise factor, impedance matching, and slew rate. Also, the effect of process, voltage, and temperature (PVT) variations are investigated. The optimum number of stages corresponding to the minimum area required for achieving a certain voltage gain is determined. The results obtained from the quantitative analysis and the simulation are discussed.

Anti-Ambipolar Transport with Large Electrical Modulation in 2D Heterostructured Devices.

Van der Waals materials and their heterostructures provide a versatile platform to explore new device architectures and functionalities beyond conventional semiconductors. Of particular interest is anti-ambipolar behavior, which holds potentials for various digital electronic applications. However, most of the previously conducted studies are focused on hetero- or homo- p-n junctions, which suffer from a weak electrical modulation. Here, the anti-ambipolar transport behavior and negative transconductance of MoTe2 transistors are reported using a graphene/h-BN floating-gate structure to dynamically modulate the conduction polarity. Due to the asymmetric electrical field regulating effect on the recombination and diffusion currents, the anti-ambipolar transport and negative transconductance feature can be systematically controlled. Consequently, the device shows an unprecedented peak resistance modulation factor (≈5 × 103 ), and effective photoexcitation modulation with distinct threshold voltage shift and large photo on/off ratio (≈104 ). Utilizing this large modulation effect, the voltage-transfer characteristics of an inverter circuit variant are further studied and its applications in Schmitt triggers and multivalue output are further explored. These properties, in addition to their proven nonvolatile storage, suggest that such 2D heterostructured devices display promising perspectives toward future logic applications.

High voltage pulse capacitor charging power supply based on double resonant topology

The pulse capacitor charging power supply is a key device in the pulse power technology. To study the higher precision high voltage pulse capacitor charging power supply, the paper analyzes the transfer function and its voltage and current transfer characteristics based on a novel double resonance topology. There are two resonance points in the double resonance circuit. According to this characteristic, a frequency modulation control method is proposed. That is, the charging phase and the high voltage holding phase, the first phase adopts the series resonant working mode, and the high voltage holding phase reduces the switching frequency to approach the second resonance point, thereby realizing dynamic compensation of the pulse capacitor self-discharge voltage drop, so that the charging accuracy and a large increase in high voltage stability of pulse capacitance at the same time can be ensured. Based on Matlab/simulink, the simulation model is built to verify the correctness of the frequency modulation method of the proposed dual resonance topology.

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.

Load-Independent Voltage and Current Transfer Characteristics of High-Order Resonant Network in IPT System

Load-independent output characteristics of an inductive power transfer (IPT) system are of increasing interest in electric vehicle and LED lighting applications. All compensation networks in the IPT system are actually high-order resonant circuits. In a high-order resonant network, there are multiple resonant frequencies to get load-independent voltage output and current output. It is critical to analyze the resonant conditions to achieve high efficiency in both load-independent voltage output and current output modes. This paper proposed a general modeling method for arbitrary high-order resonant networks to get both the load-independent voltage and current transfer characteristics. A high-order circuit can be modeled as a combination of an LC network, a multistage T-circuit, and/or multistage $\Pi $ -circuit in series. The proposed method is verified by applying to voltage-fed double-sided inductor–capacitor–capacitor (LCC), series–series (SS), S-SP, LCC-S, and current-fed CLC-LC compensation networks in the IPT system. The MATLAB simulation and the experimental prototype of a constant voltage-fed double-sided LCC compensated IPT system with up to 3.3-kW power transfer are built. The efficiency of the double-sided LCC compensated IPT system is up to 92.9% and 90.6% when the IPT system operates at resonant frequencies that achieve constant current output and constant voltage output, respectively, which are compliance with the frequency requirement by SAE J2954 standard.

Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied.

Optimisation of pocket doped junctionless TFET and its application in digital inverter

In this work, a device called pocket doped junctionless tunnel field-effect transistor (JL-TFET) for digital inverter application is proposed. The operation of this device is subjected to junctionless technique and initially it has an N+–N+–N+ structure. This device utilises a SiGe N+ pocket at the source side and a dual gate namely, fixed gate and control gate. By keeping the fixed gate voltage below its flat band voltage and varying the control gate from 0 to VDD, the device is converted from the N+–N+–N+ structure to P–I–N structure and operates like a tunnel field-effect transistor (TFET). The inclusion of N+ pocket gives an additional tunnelling path perpendicular to the gate-oxide thickness. A brief examination of the proposed device has been done on the impacts of the work-function variations of both the gate metals. A subthreshold swing of 43.6 mV/dec is obtained for fixed and control gate work-function of 5 and 4.5 eV, respectively. The proposed device gives the drain current of 5.7 × 10−4 A approximately twice that of conventional JL-TFET. Further, an radio frequency analysis of the device is done for different parameters such as drain current (ID), total gate capacitance (Cgg), transconductance (gm) and cut-off frequency (fT) and the outcomes are compared with conventional JL-TFET. The device is found to be suitable for high-frequency application. Lastly, it is applied on inverter circuit and its voltage transfer characteristics are studied.

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

Design of Low-Ripple and Fast-Response DC Filters in DC Distribution Networks

The design and parameter selection of low-ripple and fast-response direct current (DC) filters are discussed in this study with the aim of alleviating the influence of a DC-side low-frequency voltage pulsation on a sensitive load in a DC distribution network. A method for determining the DC filter parameters by using a mofatching most flat response algorithm is presented. The voltage transfer function of the DC-side filter in the DC distribution network is deduced to analyze its voltage transfer characteristics. The resonance peak value of the filter network is an important factor affecting the transfer speed of a filter. A pole-circle-based parameter optimization method is proposed to move the poles of the filter transfer function down and to the left of pole plane for finding the appropriate capacitance, inductance, and damping parameters. This approach effectively restricts the resonance peak value, accelerates the transfer speed, and maintains steady filtering results. Simulation and test results verify that the filter has low resonance value, rapid convergence ability, and an excellent filtering effect.

Improved bilayer phosphorene TFET inverter performance by reduction of ambipolarity

A comprehensive study on the degradation of inverter output voltage based on double-gated (DG) bilayer Phosphorene complementary tunnel-FETs is presented. This degradation occurs for supply voltage (VDD) larger than the bandgap value of the channel material. Simulated load-lines of n-TFET and p-TFET confirm that this degradation happens due to the high ambipolarity of homojunction DG tunnel-FETs. But ambipolarity can be suppressed effectively in both homojunction n-TFET and p-TFET using dual-material gate (DMG) structure. It is shown that by appropriately choosing the gate materials of DMG TFET, improved voltage transfer characteristics (VTC) can be obtained for DMG TFET based inverter.

Electrical Characterization of Integrated 2-Input TTL NAND Gate at Elevated Temperature, Fabricated in Bipolar SiС-Technology

This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage.The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.