Virtual Output Queuing Research Articles

THREE-STAGE CLOS-NETWORK SWITCH ARCHITECTURE WITH BUFFERED CENTER STAGE FOR MULTI-CLASS TRAFFIC

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.

Preemptive Short Packets Priority Scheduling for Asynchronous Optical Packet Switching

The average queue delay of optical packet increases when the packets block in the virtual output queue header in the asynchronous optical packet switching. We analyze the character of variable length Internet packet and propose the preemptive short packets priority (PSPP) algorithm for reducing the total packet queue time in the queue. In the PSPP algorithm, the short packet can preempt the transmission time of the long packet and can be served first. The analysis and the simulation showed the PSPP algorithm can make the average queue time of the short packet decrease to zero almost and can decrease the total packet average queue time largely when the traffic load was middle and low. The PSPP could guarantee the low average queue delay for the real -time TCP traffic.

Design and performance analysis of scheduling algorithms for WDM-PON under SUCCESS-HPON architecture

Results of the design and performance analysis of two new algorithms for efficient and fair scheduling of variable-length frames in a wavelength division multiplexing (WDM)-passive optical network (PON) under the Stanford University aCCESS-Hybrid PON (SUCCESS-HPON) architecture are reported. The WDM-PON under the SUCCESS-HPON architecture has unique features that have direct impacts on the design of scheduling algorithms. First, an optical line terminal (OLT) uses tunable transmitters and receivers that are shared by all the optical network units (ONUs) served by the OLT to reduce the number of expensive dense WDM (DWDM) transceivers. Second, also for cost reduction, ONUs have no local DWDM light sources but use optical modulators to modulate optical continuous wave (CW) bursts provided by the OLT for upstream transmissions. Therefore, the tunable transmitters at the OLT are used for both upstream and downstream transmissions. To provide efficient bidirectional communications between the OLT and the ONUs and guarantee fairness between upstream and downstream traffic, two scheduling algorithms have been designed: 1) batching earliest departure first (BEDF); and 2) sequential scheduling with schedule-time framing (S/sup 3/F). The BEDF is based on the batch scheduling mode where frames arriving at the OLT during a batch period are stored in virtual output queues (VOQs) and scheduled at the end of the batch period. It improves transmission efficiency by selecting the frame with the earliest departure time from a batch of multiple frames, which optimizes the usage of tunable transmitters in scheduling. Considering the high complexity of the optimization process in BEDF, the S/sup 3/F based on the sequential scheduling mode has also been designed as in the original sequential scheduling algorithm proposed earlier. In S/sup 3/F, the authors use VOQs to provide memory space protection among traffic flows and a granting scheme together with schedule-time framing for both upstream and downstream traffic to reduce framing and guard band overhead. Through extensive simulations under various configurations of the tunable transmitters and receivers, it has been demonstrated that both the BEDF and S/sup 3/F substantially improve the throughput and delay performances over the original sequential scheduling algorithm, while guaranteeing better fairness between upstream and downstream traffic.

On the Combined Input-Crosspoint Buffered Switch With Round-Robin Arbitration

Input-buffered switches have been widely considered for implementing feasible packet switches. However, their matching process may not be time-efficient for switches with high-speed ports. Buffered crossbars (BXs) are an alternative to relax timing for packet switches with high-speed ports and to provide high-performance switching. BX switches were originally considered expensive, as the memory amount required in the crosspoints (XPs) is proportional to the square of the number of ports (O(N/sup 2/)). This limitation is now less stringent with the advances on chip-fabrication techniques, and when considering small crosspoint (XP) buffer sizes. In this paper, we study a combined input-crosspoint buffered packet switch, named CIXB, with virtual output queues (VOQs) at the inputs, and arbitration based on round-robin selection. We show that the CIXB switch achieves 100% throughput under uniform traffic, and high performance under nonuniform traffic, using one-cell XP buffer size and no speedup.

FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches

Many networking/computing applications require high speed switching for multicast traffic at the switch/router level to save network bandwidth. However, existing queuing-based packet switches and scheduling algorithms cannot perform well under multicast traffic. While the speedup requirement makes the output queued switch difficult to scale, the single input queued switch suffers from head of line (HOL) blocking, which severely limits the network throughput. An efficient yet simple buffering strategy to remove the HOL blocking is to use the virtual output queued (VOQ) switch structure, which has been shown to perform well under unicast traffic. However, the traditional VOQ switch is impractical for multicast traffic because a VOQ switch for multicast traffic has to maintain an exponential number of queues in each input port (i.e., 2/sup N/-1 queues for a switch with N output ports). In this paper, we give a novel queue structure for the input buffers of a multicast VOQ switch by separately storing the address information and data information of a packet so that an input port only needs to manage a linear number (N) of queues. In conjunction with the multicast VOQ switch, we present a first-in-first-out based multicast scheduling algorithm, FIFO multicast scheduling (FIFOMS), and conduct extensive simulations to compare FIFOMS with other popular scheduling algorithms. Our results fully demonstrate the superiority of FIFOMS in both multicast latency and queue space requirement.

High-performance switching based on buffered crossbar fabrics

As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained a lot of interest recently due to their great potential in solving the complexity and scalability issues faced by their buffer-less predecessors. The IBC switching architecture combined with the virtual output queueing (VOQ) architecture was shown, through distributed scheduling algorithms, to be able to sustain the current and expected increases in Internet throughput rates. Due to the architectural similarity between the input queued (IQ) and IBC switches, all the algorithms proposed for the latter were just a simple mapping of earlier algorithms proposed for the former. In this paper, we propose a set of scheduling schemes that are purely advocated for the VOQ/IBC switch architecture. We first address the issue of the internal buffers importance in the arbitration process. We propose a weighted scheduling algorithm, named Critical internal Buffer First (CBF), which takes full advantage of the internal buffer elements and makes its decision exclusively on the internal buffer information. Second, in order to simplify the scheduling scheme and make it practical, we propose a class of scheduling algorithms, named Current Arrival First–Priority Removal (CAF–PRMV) that use priority levels instead of weights. We argue that the interaction, through the internal buffer element, between the input and output schedulers is very important in designing such practical and highly scalable schemes for the IBC switching architecture. Our hardware implementation, in reconfigurable logic, shows that our CAF–PRMV class of algorithms can sustain a 10 Gbps line speed for a 32 × 32 VOQ/IBC switch.

Integration of unicast and multicast scheduling in input-queued packet switches

Packet queuing and scheduling, two of the critical components in an input-queued packet switch, have been extensively studied in the context of either pure unicast traffic or pure multicast traffic. Unfortunately, the results from a study in one context are not applicable to the other context. The design of integrated scheduling for both types of traffic remains an open issue. This paper deals with the problem of integrating unicast and multicast scheduling in an N × N input-queued packet switch with first in first out buffers. Instead of using isolated switching fabrics for unicast and multicast traffic respectively, we efficiently utilize one switching fabric for both unicast and multicast traffic by a careful design. In our design, each input port maintains a set of unicast queues based on virtual output queuing technique and a set of multicast queues based on a load-balance policy. By employing the research advances that have already been gained for unicast and multicast scheduling, we propose two practical slot-coupled integration algorithms, lSCIA (a loosely slot-coupled integration algorithm) and fSCIA (a fully slot-coupled integration algorithm). In each time slot, unicast scheduling and multicast scheduling cooperate together and the scheduling priority is allocated to either unicast traffic or multicast traffic according to a certain service ratio. The working interval of service ratio is defined as a set such that the saturation throughput is not less than the output load if the service ratio falls into this set. The upper bound and lower bound for the working interval of service ratio are deduced. A 100% throughput can be achieved with strong theoretical guarantees as long as the service ratio lies in the upper bound of the working interval. Both theoretical analysis and simulation studies suggest that the proposed integrated scheduling algorithms exhibit a promising performance in terms of throughput, delay and packet loss ratio, at different traffic compositions under Bernoulli traffic and bursty traffic.

Stability analysis of input-buffered packet switches with maximal size matching

We analyze the stability of input-buffered packet switches with virtual output queue (VOQ), maximal size matching (MSM) algorithm and speedup. We first introduce a queueing system for the stability analysis. Using supplementary variables to represent the packet switching mode and remaining packet service time, we describe the behavior of the queueing system. Then, we propose a Lyapunov function to prove speedup of 2 is sufficient to achieve 100 % throughput in input-buffered packet switches with MSM algorithm.

Reliable control protocol for crossbar arbitration

We describe an incremental request-grant protocol between line cards comprising virtual output queues and a central arbitration unit in a crossbar-based packet switch. Moreover, we introduce a method to make this protocol reliable in the presence of transmission errors that might lead to permanent inconsistency of the queue state information maintained by the arbiter. The protocol employs a census mechanism that travels the round-trip distance from line card to arbiter and back. We prove that it detects any inconsistency as well as its precise magnitude, enabling immediate corrective action.

Benes switching fabrics with O(N)-complexity internal backpressure

Multistage buffered switching fabrics are the most efficient method for scaling packet switches to very large numbers of ports. The Benes network is the lowest-cost switching fabric known to yield operation free of internal blocking. Backpressure inside a switching fabric can limit the use of expensive off-chip buffer memory to just virtual-output queues in front of the input stage. This article extends the known credit-based flow control (backpressure) architectures to the Benes network. To achieve this, we had to successfully combine per-flow backpressure, multipath routing (inverse multiplexing), and cell resequencing. We present a flow merging scheme that is needed to bring the cost of backpressure down to O(N) per switching element, and for which we have proved freedom from deadlock for a wide class of multipath cell distribution algorithms. Using a cell-time-accurate simulator, we verify operation free of internal blocking, evaluate various cell distribution and resequencing methods, compare performance to that of ideal output queuing, the iSLIP crossbar scheduling algorithm, and adaptive and randomized routing, and show that the delay of well-behaved flows remains unaffected by the presence of congested traffic to oversubscribed output ports.

Performance analysis of large multicast switches with multicast virtual output queues

In multicast switches, the accommodation of multicast traffic in multiple queues per input buffer reduces the throughput degradation caused by head-of-line (HOL) blocking. Such an arrangement, called multicast virtual output queuing (MC-VOQ), is very promising in theory but can only be implemented in practice with heavy approximation. Complete avoidance of the HOL blocking problem would in fact require a distinct queue for each fanout set possible, leading to an exponential growth of the number of queues needed with the switch size. If only a limited number of queues can be used per input buffer, criteria must be identified for setting the number of queues, for associating the fanout sets with the individual queues, and for scheduling the transmission of packets out of the queues. This paper presents an analytical model for the investigation of saturation throughput and packet delay in MC-VOQ multicast switches. The model relies on the assumption of Poisson-distributed uniform input traffic and random queuing and scheduling policies. Extensive simulation experiments validate the results of the analysis for large switch sizes.

Performance evaluation of new scheduling methods for the RR/RR CICQ switch

Increasing link speeds and port counts in packet switches demand that methods for minimizing internal speed-up and implementing fast scheduling be developed. Combined input and cross point queued (CICQ) switches with round-robin (RR) polling of virtual output queues (VOQ) and of cross point buffers can natively forward variable-length packets without a required internal segmentation into cells. However, native switching of variable-length packets results in unfairness between ports. To eliminate this unfairness, we propose a block transfer mechanism that transfers up to a predefined number of bytes of packet data from a selected VOQ. This mechanism does not require internal speed-up. We also propose an overlapped RR (ORR) arbiter design that fully overlaps RR polling and scheduling. Using simulation and both synthetic and traced packet traffic as input, we show that the RR/RR CICQ switch with the block transfer mechanism has a lower delay than an input queued (IQ) switch that internally uses cells. We also show that the ORR arbiter is scalable, work conserving, and fair.

A scheduling scheme for variable‐length packets in an input‐buffered ATM switch with priority of active buffer

AbstractIn ATM (asynchronous transfer mode) we propose a VOQ (virtual output queuing) switch in which the same number of buffers as the number of output ports are provided in each input port, serving as an input‐buffered switch to avoid HoL (head of line) blocking. In addition, in order to handle the recent increase of IP traffic, the IP‐PIM (IP‐parallel iterative matching) scheme is proposed as the scheduling scheme for the VOQ switch using variable‐length packets. However, the IP‐PIM scheme has the problem that the queue lengths in other buffers are increased, since cells belonging to the same packet are always handled continuously, which degrades the packet loss probability. Consequently, this paper proposes a scheduling scheme with active buffer priority in which the buffer receiving the cells belonging to the packet under consideration is defined as the active buffer and is given priority. In the proposed scheme, the queue length is reduced by giving the priority to the active buffer, and efficient switching is realized. The packet loss probability and the average packet delay are evaluated by computer simulation. It is found that the proposed scheme can greatly improve the packet loss probability compared to the conventional scheme, with degradation of the average packet delay by approximately 20 slots. It is also shown that a satisfactory loss probability is realized even if the buffer size is small, and that good expandability with regard to the switch size is achieved. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 87(2): 79–90, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10120

On achieving throughput in an input-queued switch

We establish some lower bounds on the speedup required to achieve throughput for some classes of switching algorithms in a input-queued switch with virtual output queues (VOQs). We use a weak notion of throughput, which will only strengthen the results, since an algorithm that cannot achieve weak throughput cannot achieve stronger notions of throughput. We focus on priority switching algorithms, i.e., algorithms that assign priorities to VOQs and forward packets of high priority first. We show a lower bound on the speedup for two fairly general classes of priority switching algorithms: input priority switching algorithms and output priority switching algorithms. An input priority scheme prioritizes the VOQs based on the state of the input queues, while an output priority scheme prioritizes the VOQs based on their output ports. We first show that, for output priority switching algorithms, a speedup S/spl ges/2 is required to achieve weak throughput. From this, we deduce that both maximal and maximum size matching switching algorithms do not imply weak throughput unless S/spl ges/2. The bound of S/spl ges/2 is tight in all cases above, based on a result in Dai et al. Finally, we show that a speedup S/spl ges/3/2 is required for the class of input priority switching algorithms to achieve weak throughput.

An evolution to crossbar switches with virtual output queuing and buffered cross points

Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem.

Performance Evaluation of Crossbar Switch Fabrics in Core Routers

Many researchers have pointed out that using complex scheduling algorithms in input queuing switches with virtual output queuing (VOQ) scheme can achieve 100% throughput. But these algorithms are too complex to be implemented in hardware. In this paper, based on combined input/output queuing (CIOQ) switch fabrics, we propose a simple scheduling algorithm named outlet priority round robin (OPRR). For synthetic workloads we consider, including uniform and bursty traffic models, the performance of OPRR in VOQ mode and single queue mode is evaluated respectively. Through the simulation results we show that 1) OPRR algorithm, coupled with the speedup of 2, can lead to performance very close to output queuing switches, and 2) under the same condition, OPRR algorithm in single queue mode behaves almost identically to VOQ mode. These results are very useful to direct the design and implementation of switch fabrics in core routers.

Cell scheduling for VOQ switches with different strict priority levels

Scheduling algorithms developed for virtual-output-queuing (VOQ) switches have focused on the throughput enhancement, rather than provide QoS guarantees for different priority levels. Presented, is a new scheduling scheme to effectively support real-time and data applications in VOQ switches with negligible complexity increment.

Gemini: an optical interconnection network for parallel processing

The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightly-coupled multicomputer systems. It consists of a circuit-switched optical data path in parallel with a packet-switched electrical control/data path. The optical path is used for transmission of long data messages and the electrical path is used for switch control and transmission of short data messages. The paper describes the architecture of the interconnection network and related communications protocols. Fairness issues associated with network operation are addressed and a discrete-event simulation model of the entire system is described. Network performance characteristics derived from the simulation model are presented. The results show significant performance benefits when using virtual output queuing and quantify the tradeoffs between throughput and fairness in the system.

Analysis of non-uniform cell destination distribution in virtual output queueing systems

We develop a discrete-time analytical queueing model for studying the performance of input-queued switches with non-uniform cell destination distribution. Virtual output queues are assumed at the ingress ports where cell arrivals are geometrically distributed and the service process is based on a work conserving random selection scheme. We consider the conditions for stability as basis for deriving closed-form expressions for the stationary queue size distributions from which the mean queue sizes and mean cell latencies are derived. We show that a very good agreement is obtained between simulation and analytical results.

Port partitioning and dynamic queueing for IP forwarding

With the increase of internet protocol (IP) packets the performance of routers became an important issue in internet/working. In this paper we examine the matching algorithm in gigabit router which has input queue with virtual output queueing. Dynamic queue scheduling is also proposed to reduce the packet delay and packet loss probability. Port partitioning is employed to reduce the computational burden of the scheduler in a switch which matches the input and output ports for fast packet switching. Each port is divided into two groups such that the matching algorithm is implemented within each pair of groups in parallel. The matching is performed by exchanging the pair of groups at every time slot. Two algorithms, maximal weight matching by port partitioning (MPP) and modified maximal weight matching by port partitioning (MMPP) are presented. In dynamic queue scheduling, a popup decision rule for each delay critical packet is made to reduce both the delay of the delay critical packet and the loss probability of loss critical packet. Computational results show that MMPP has the lowest delay and requires the least buffer size. The throughput is illustrated to be linear to the packet arrival rate, which can be achieved under highly efficient matching algorithm. The dynamic queue scheduling is illustrated to be highly effective when the occupancy of the input buffer is relatively high. Scope and purpose To cope with the increasing internet traffic, it is necessary to improve the performance of routers. To accelerate the switching from input ports to output in the router partitioning of ports and dynamic queueing are proposed. Input and output ports are partitioned into two groups A/B and a/b, respectively. The matching for the packet switching is performed between group pairs (A, a) and (B, b) in parallel at one time slot and (A, b) and (B, a) at the next time slot. Dynamic queueing is proposed at each input port to reduce the packet delay and packet loss probability by employing the popup decision rule and applying it to each delay critical packet. The partitioning of ports is illustrated to be highly effective in view of delay, required buffer size and throughput. The dynamic queueing also demonstrates good performance when the traffic volume is high.