Virtex-5 Field Programmable Gate Array Research Articles

FPGA-Based Implementation of Multidimensional Reconciliation Encoding in Quantum Key Distribution.

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s.

Programmable implementation of time-area-efficient Elliptic Curve Cryptography for entity authentication

In the ever increasing wireless reliant technologies, communications and devices, the demand for effective security with low hardware and high speed is wanting in the cryptography domain. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system Authentication process using the ECC has been implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication has been performed with the faster multiplier Urdhva Tiryagbhyam. Additionally, pipelining has been incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, area-delay product and throughput. Hence, the implementation of the proposed method offers time-area-efficient fast scalar multiplication with effective hardware utilization without any compromise in security level.

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by the homomorphic multiplication, especially the polynomial multiplication which occupies major computing resources. Therefore, efficient implementation of polynomial multiplication is crucial for high-performance FHE applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), which employs NTT and INTT for polynomial multiplier with a variable number of reconfigurable processing elements. To reduce latency, MCNA merges the preprocessing and postprocessing into the constant-geometry NTT and INTT, respectively. Also, a reconfigurable modular multiplier based on digital signal processor (DSP) is proposed to speed up the modular multiplication. In order to avoid designing independent memory access pattern for INTT, a unified read/write structure of NTT/INTT is presented. Furthermore, a novel memory access pattern named “cyclic-sharing” is proposed to reduce 25% memory capacity. MCNA is evaluated on a Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, the throughput of MCNA for NTT/INTT achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.78\times \sim 9.32\times $ </tex-math></inline-formula> improvements in comparison to prior works, while the area efficiency of lookup table (LUT) and flip-flop (FF) is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25\times \sim 4.79\times $ </tex-math></inline-formula> . For polynomial multiplication, the throughput of MCNA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.73\times \sim 7.69\times $ </tex-math></inline-formula> enhancements, as well as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.13\times \sim 14.8\times $ </tex-math></inline-formula> area efficiency improvements.

Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform

The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.

Low-area and high-speed hardware architectures of LBlock cipher for Internet of Things image encryption

Security is becoming an essential field of research as network technology is changing at a rapid pace. Digital images are transmitted in many modes of communication. This transmission must be secure, particularly in applications that demand a high level of security, such as military applications, surveillance, radars, and biometrics. Two hardware solutions of the lightweight block cipher LBlock are provided to secure image data. These proposed architectures are implemented on a Xilinx field programmable gate arrays (FPGA) platform, and the implementation results are compared with existing state-of-the-art designs. The proposed designs took 56 and 64 slices operating at a frequency of 492.441 and 681.663 MHz, respectively, on a Virtex-5 FPGA platform. In addition, the proposed round-based and pipelined designs showed improvement in hardware efficiency over state-of-the-art designs. The proposed hardware architectures are capable of securing different sizes of gray-scale and RGB color images. These hardware solutions were verified by different analyses, including correlation coefficient, mean square error (MSE), peak signal-to-noise ratio (PSNR), histogram, entropy, number of pixel changing rate (NPCR), and unified average changing intensity (UACI). The existing solutions were compared with correlation coefficients, NPCR, UACI, MSE, PSNR, and entropy values and provide better solutions than the state-of-the-art designs.

An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors

The continuous technology scaling of integrated circuits results in increasingly higher power densities and operating temperatures. Hence, modern many-core processors require sophisticated thermal and resource management strategies to mitigate these undesirable side effects. A simulation-based evaluation of these strategies is limited by the accuracy of the underlying processor model and the simulation speed. Therefore, we present, for the first time, an field-programmable gate array (FPGA)-based evaluation approach to test and compare thermal and resource management strategies using the combination of benchmark generation, FPGA-based application-specific integrated circuit (ASIC) emulation, and run-time monitoring. The proposed benchmark generation method enables an evaluation of run-time management strategies for applications with various run-time characteristics. Furthermore, the ASIC emulation platform features a novel distributed temperature emulator design, whose overhead scales linearly with the number of integrated cores, and a novel dynamic voltage frequency scaling emulator design, which precisely models the timing and energy overhead of voltage and frequency transitions. In our evaluations, we demonstrate the proposed approach for a tiled many-core processor with 80 cores on four Virtex-7 FPGAs. Additionally, we present the suitability of the platform to evaluate state-of-the-art run-time management techniques with a case study.

A reconfigurable PUF structure with dual working modes based on entropy separation model

Privacy Protection Mutual Authentication (PPMA) in the Internet of Things uses physical unclonable functions (PUFs) and true random number generators (TRNGs) as security primitives, providing a lightweight solution for key generation and protection. At present, the designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) lack theoretical support, and have poor randomness and stability. Therefore, this paper provides a separation model of PUF entropy (manufacturing delay) and TRNG entropy (jitter delay) based on ring oscillators (ROs). Based on this model, a reconfigurable PUF structure is proposed, which can be reconstructed to a TRNG by changing the working mode. The proposed structure not only improves the area utilization, but also realizes the low-power consumption. Experiments on Xilinx Spartan-6 FPGAs and Xilinx Virtex-6 FPGAs show that the proposed structure has wonderful performance. The PUF has excellent uniqueness (average resolution is 50.21%) and reliability (the average repeatability rate is 96.98%). TRNG's output sequences have high randomness and pass all National Institute of Standards and Technology (NIST) tests (average pass rate is 99%).

An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA

This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-parallel multiplier in the proposed design results in high-speed (in terms of both clock frequency and latency). Consequently, the proposed BHC architecture, integrated with a least-significant-digit-parallel multiplier, is 1.42 times faster and utilizes 1.80 times lower FPGA slices when compared to the most recent BHC accelerator architectures.

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

Performance Analysis of AODV Routing for Wireless Sensor Network in FPGA Hardware

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flip-flops, and memory for the different configurations of the network (N = 10, 20 ….100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes.

Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate rotation digital computer (CORDIC) algorithm has read-only memory (ROM)-based architecture to store FFT twiddle factors and their angle generators. The address generation unit is required to fetch the data and write the results into the memory in the appropriate sequence. CORDIC provides low memory, delay, and optimized hardware on the field-programmable gate array (FPGA) in comparison to normal FFT architecture for the OFDM system. The comparative performance of the FFT and CORDIC-FFT based OFDM transceiver chip is estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, and delay. The design is developed using integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized using very-high-speed integrated circuit hardware description language (VHDL), and tested on Virtex-5 FPGA.

Smart Communication Using 2D and 3D Mesh Network-on-Chip

Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication.

FPGA Implementation of Elliptic-Curve Diffie Hellman Protocol

This paper presents an efficient crypto processor architecture for key agreement using ECDH (Elliptic-curve Diffie Hellman) protocol over . The composition of our key-agreement architecture is expressed in consisting of the following: (i) Elliptic-curve Point Multiplication architecture for public key generation (DESIGN-I) and (ii) integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation (DESIGN-II). The arithmetic operators used in DESIGN-I and DESIGN-II contain an adder, squarer, a multiplier and inversion. A simple shift and add multiplication method is employed to retain lower hardware resources. Moreover, an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units. The proposed architecture is implemented in a Verilog HDL. The implementation results are given on a Xilinx Virtex-7 FPGA (field-programmable gate array) device. For DESIGN-I and DESIGN-II over , (i) the utilized Slices are 3983 and 4037, (ii) the time to compute one public key and a shared secret is 553.7 μs and 1170.7 μs and (iii) the consumed power is 29 μW and 57 μW. Consequently, the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative (to generate a shared secret) for the applications that require low hardware resources and power consumption.

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

Medical Image Demosaicing Based Design of Newton Gregory Interpolation Algorithm

In this paper, Field-Programmable Gate Array (FPGA) implementation-based image demosaicing is carried out. The Newton Gregory interpolation algorithm is designed based on FPGA frame work. Interpolation is the method of assessing the value of a function for any in-between value of self-regulating variable, whereas the method of computing the value of the function outside the specified range is named extrapolation. The natural images are collected from Kodak image database and medical images are collected from UPOL (University of Phoenix Online) database. The proposed algorithm is executed on using Xilinx ISE (Integrated Synthesis Environment) Design Suite 14.2 and is confirmed on Xilinx Virtex-5 FPGA board. The main aim of this paper is to develop a demosaicing method based on the FPGA technique. Implementing image processing on hardware reduces the cost and make simpler for debugging and verification. The hardware implementation in this system gives the better quality of output image. Implementing image processing on hardware reduces the cost and makes simpler for debugging and verification. Newton- Gregory interpolation technique produces the full resolution of green channel with red and blue channels. The experimental result clearly shows that proposed Newton-Gregory interpolation-based image demosaicing outperformed other algorithms. FPGA implementation attains the maximum Peak Signal-To-Noise Ratio (PSNR) of 40.53 dB and MATLAB (Matrix Laboratory<b>)</b>. implementation attains the maximum PSNR of 38.15 dB.

FPGA Hardware in the Loop Validation of Asynchronous Machine with Full Direct Torque Control Implementation

This article provides a full hardware implementation for direct torque control (DTC) of an asynchronous motor (AM) on the Field Programmable Gate Array (FPGA). Due to its high processing frequency, the FPGA circuit presents an alternative for achieving a high performance DTC implementation. This cannot be achieved by any DSP or microcontroller application. The proposed hardware architecture implements three components of DTC control strategy (the integral proportional speed regulator, the estimation and the switching blocks). This implementation has the advantage of being faster, more efficient and with minimum hardware resources on the target FPGA board. The hardware architecture of the DTC control was designed and simulated in Matlab / Simulink using XSG blocks, then synthesized with the Xilinx ISE 14.2 tool, implemented and validated on the Xilinx Virtex-4 FPGA circuit by Hardware in the Loop process.

A digital direction of arrival estimator based on fast on-line sequential random vector functional link network

This article develops a fast online sequential random vector functional network. In this network, input nodes are connected to both hidden nodes and output nodes. This architecture results in high-speed learning and testing. The network estimates the direction of arrival from signals received by the sparse array in real-time. Neither noisy signal nor effect of mutual coupling among array elements affect the estimation appreciably using the network. The network shows competitive performance in terms of learning speed, accuracy, short event regression time, simplicity, and robustness in comparison to other state-of-the-art methods such as support vector regression, extreme learning machine, and online sequential extreme learning machine. Finally, validation of the network translation into a hardware platform using a fast digital high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array embedded processor for single-source detection completes the work. Comparison with reported measurement shows results with good accuracy and low root mean square error both by the network and its hardware-implemented platform. The direction of arrival estimation is thus possible using the network either through a computer or dedicated hardware as per necessity.

A field programmable gate array-based biomedical noise reduction framework using advanced trilateral filter

Filtering is one of the essential tools utilized to remove undesirable features in biomedical images. Most biomedical image denoising systems are used for clinical diagnosis. So, in this paper, we use the advanced trilateral filter in the field programmable gate array (FPGA) for removing noise in the biomedical image. Generally, the trilateral filter is used as an edge preserving smoothing filter. This advanced approach of trilateral filter gives the best noise diminution and enhances the image quality. This paper also proposes the hardware implementation of an efficient FPGA-based advanced trilateral filter on real time execution. In this manuscript, we intend to design and implement the FPGA architecture using an advanced trilateral filter. Biomedical images with different noises are used during implementation and compared with the existing bilateral and trilateral architecture to assess the proposed architecture performance. For evaluating the performance metrics of the proposed advanced trilateral filter on MATLAB platform, peak signal-to-noise ratio (PSNR), mean squared error (MSE) and structured similarity index (SSIM) are calculated for different biomedical images – such as brain (MRI), chest (x-ray) and lungs (CT) – with different noises – such as salt and pepper, Gaussian, Poisson and Speckle noises – compared with existing bilateral filter and trilateral filter, respectively. The proposed advanced trilateral filter implementations are checked on Virtex-6, Virtex-7 and Zynq FPGA development board using Verilog programming language in Xilinx ISE 14.5 design tools. The simulation outcomes display that the FPGA execution of the advanced trilateral filter contains better noise removal efficiency in biomedical images compared with the existing bilateral and trilateral filter.

Onboard target detection in hyperspectral image based on deep learning with FPGA implementation

Onboard target detection of Hyperspectral Imagery (HSI) is widely adopted in the field of remote sensing. It requires high detection accuracy and low computational complexity for processing a large volume of HSI data. In this study, a Locally Preserving Discriminative Broad Learning (LPDBL) was introduced for target detection due to its simple, excellent generalization ability, and its competitive performance. The detection was done through spatial-spectral information, band selection, and estimation of the covariance matrix. The fisher discriminant method was used to reduce the dimension of HSI data. Weights was adjusted through manifold regularization in order to enhance the detection ability of the proposed method. To study the performance of the proposed LPDBL, experiment was conducted on two different datasets of HSI. The results revealed that the proposed method performed better and suitable for target detection. The LPDBL was implemented on Virtex-7 Field Programmable Gate Array (FPGA) board. Furthermore, the LPDBL technique was practically validated by two different techniques such as a broad learning system (BLS) and Automatic Target Detection in HSI (ATD-HSI). The result obtained from the FPGA was very close to the actual target position.