Video Graphics Array Research Articles

Portable multi‐gray scale video playing scheme for high‐performance electrowetting displays

AbstractElectrowetting display technology is realized by tuning the surface energy of a hydrophobic surface by applying a voltage based on electrowetting mechanism. Electrowetting displays have favorable optical properties combined with reflective paper‐like performance. It has been successfully demonstrated in reflective mode with high switching speed. In this paper, we propose a portable driving scheme that can display 4‐bit gray scale dynamic video using an active matrix electrowetting display. The proposed driving scheme includes an electronic system and a dynamic driving waveform design. High‐performance multi‐gray video playing and quick response were obtained for a Quarter Video Graphics Array electrowetting display cell fabricated by our team.

A Novel Wavefront-Based High Parallel Solution for HEVC Encoding

With a lot of enhanced coding tools introduced, High Efficiency Video Coding (HEVC) achieves significant improvement in coding efficiency at the cost of increased computational complexity. To efficiently reduce the encoding time of HEVC, a wavefront-based high parallel (WHP) solution integrating novel data-level and task-level methods is proposed in this paper. On data level, optimal single-instruction-multiple-data algorithms are designed for the enhanced coding tools, i.e., replacing the multiplication in motion compensation by add and shift operations with reduced instruction cycles, removing the transpose in transform via realignment of coefficients, and minimizing the memory access in sum of absolute difference/sum of squared differences calculation by fully reusing the registers. On task level, a novel inter-frame wavefront (IFW) method is developed by effectively decreasing the dependence of wavefront parallel processing (WPP). In addition, a coding tree block level parallelism analysis method is presented to prove the superior of IFW method compared with other HEVC representative parallel methods. Besides, a three-level thread management scheme is proposed to best exploit the parallelism of IFW method and achieve corresponding encoding speedup. Extensive experimental results show that, the overall WHP solution can bring up to $57.65\times $ , $65.55\times $ , and $88.17\times $ speedup for HEVC encoding of Wide Video Graphics Array, 720p and 1080p standard test sequences, while maintaining the same coding performance as with WPP. The proposed solution is also applied in several leading video companies in China, providing HEVC video service for more than 1.3 million users everyday.

Color Transparent Display Using Polymer-Dispersed Liquid Crystal

We have developed a 11.4-inch color active-matrix thin-film transistor (TFT) transparent liquid crystal display (LCD) by using polymer-dispersed liquid crystal (PDLC) technology. The resolution of color transparent LCD was designed to wide screen video graphics array (WSVGA) and the pixel per inch (PPI) is 104. Then, the transmittance of the color transparent LCD can achieve upward 15%. In this paper, the color transparent display has some advantages, such as, good visibility, high transparency, polarizer free, backlight less (environmental light only), and so on.

A SPAD-Based QVGA Image Sensor for Single-Photon Counting and Quanta Imaging

A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

Real-time mid-infrared imaging of living microorganisms.

The speed and efficiency of quantum cascade laser-based mid-infrared microspectroscopy are demonstrated using two different model organisms as examples. For the slowly moving Amoeba proteus, a quantum cascade laser is tuned over the wavelength range of 7.6 µm to 8.6 µm (wavenumbers 1320cm(-1) and 1160cm(-1) , respectively). The recording of a hyperspectral image takes 11.3s whereby an average signal-to-noise ratio of 29 is achieved. The limits of time resolution are tested by imaging the fast moving Caenorhabditis elegans at a discrete wavenumber of 1265cm(-1) . Mid-infrared imaging is performed with the 640 × 480 pixel video graphics array (VGA) standard and at a full-frame time resolution of 0.02 s (i.e. well above the most common frame rate standards). An average signal-to-noise ratio of 16 is obtained. To the best of our knowledge, these findings constitute the first mid-infrared imaging of living organisms at VGA standard and video frame rate.

Paper No S16.1: SVGA Bidirectional OLED Microdisplay for Near‐to‐Eye Projection

AbstractThe bidirectional microdisplay approach combines organic light‐emitting diode (OLED) image display and silicon complementary metal‐oxide‐semiconductor image sensing in a single chip. Its application in smart glasses might enable gaze‐controlled interaction. This is to present a new bidirectional OLED microdisplay featuring super video graphics array resolution for both image display and acquisition.

FPGA Implementation of Hiding Information using Cryptography

Background: The main threat in communication is the unauthorized access of information third party without the knowledge of sender and receiver. Hence the security plays a vital role in data transmission systems. Confidential data like internet banking account passwords and email account passwords needs security in their text data. Data can be text, image, video and audio. Methods: The purpose of this research work is to implement a mechanism to hide information (image) using cryptography. Advanced Encryption Standard (AES) is a type of symmetric cryptography standard which can be used to transfer a block of information securely during transmission. Findings: The idea of this paper is to generate an encrypted image by giving image input to AES encryption system and getting the decrypted image as original image by giving encrypted image as input to the AES decryption system. The input image is given through MATLAB R2012b to ModelSim6.3 and the system simulation and synthesis is done by integrating Model Sim to the Altera DE2 115 board through Quartus II software. Conclusion: The maximum frequency attained from this workis 165.462MHz. Finally image is displayed through an LCD which is connected to the board using Video Graphics Array (VGA) Connector.

Box, cable and smartphone: a simple laparoscopic trainer.

Laparoscopic surgery requires different abilities to open surgery, and is challenging to learn within the confines of the operating theatre. With the development of laparoscopic surgery in modern surgery, the importance in improving these skills is becoming an increasing focus of surgical training programmes. The assembly of the laparoscopic trainer and exercises was performed at the University of Sydney Clinical School located at Hornsby Hospital in Sydney, Australia. The objective was to design and construct a new concept smartphone box laparoscopic trainer that is affordable and replicable, and to demonstrate its usefulness in practising laparoscopic techniques to improve skills outside of the operating theatre. The trainer was constructed using a personal smartphone, cardboard box, video graphics array (VGA) adaptor, VGA cable and a computer screen. Laparoscopic instruments and materials used for simulated task exercises were obtained from the operating theatre. Simulated demonstrations of simple laparoscopic tasks included suture handling, instrument knot-tying and anastomotic suture techniques. The smartphone box trainer is inexpensive (approximately $60) and took less than 20minutes to build. The cost was almost entirely for the VGA adaptor. The box trainer was light, portable and easily transported to any setting that provided a computer screen. It is an inexpensive, easy-to-assemble, replicable model that benefits from the advanced technology of personal smartphones, and can be easily accessed as a useful tool in learning and improving laparoscopic techniques. Laparoscopic surgery requires different abilities to open surgery.

High Performance Top‐Emitting Organic Light‐Emitting Diodes for Super Video Graphics Array Monochromatic Microdisplays Application

AbstractWe have demonstrated a high performance top‐emitting organic light‐emitting diode (TEOLED) achieving a brightness of 1000 cd/m2 at a low voltage of 3.4 V, a power efficiency of 55.2 lm/W at a brightness of 611 cd/m2, and a low efficiency roll‐off 5.1% calculated from the maximum efficiency value to that of 5000 cd/m2. Such improved properties are controlled by electron injection from 7‐diphenyl‐1,10‐phenanthroline (BPhen) into and transport by the 2,4,6‐tris[3′‐(pyridin‐3‐yl)biphenyl‐3‐yl]‐1,3,5‐triazine (TmPPPyTz) layer along with hole injection from 4,4′,4′′‐tris(N‐carbazolyl)diphenylamine (TcTa) directly into the fac‐tris(2‐phenylpyridine)iridium [Ir(ppy)3] highest occupied molecular level (HOMO), leading to direct carrier recombination and excitons formation on the phosphor dopants. Eventually we integrated our high performance TEOLEDs on complementary metal oxide semiconductor (CMOS) substrates to realize super video graphics array (SVGA) OLED microdisplays.

Latest Developments in Long-Wavelength and Very-Long-Wavelength Infrared Detection with p-on-n HgCdTe

We report recent developments at Commissariat a l’Energie Atomique-Laboratoire d’Electronique des Technologies de l’Information Infrared Laboratory on the processing and characterization of p-on-n HgCdTe (MCT) planar infrared focal plane arrays (FPAs) operating in the long-wavelength infrared (LWIR) and very-long-wavelength infrared (VLWIR) spectral bands. The active layers in these FPAs were grown by liquid phase epitaxy (LPE) on a lattice-matched CdZnTe substrate. This technological process results in lower dark current and lower serial resistance than for n-on-p vacancy-doped architecture and thus is better adapted for lower flux detection or higher operating temperature. This architecture was evaluated for space applications in the LWIR and VLWIR spectral bands with cutoff wavelengths from 10 to 17 μm at 78 K. Innovations have been introduced to the technological process to form a heterojunction by use of an LPE growth technique. The initial objective was to reduce the dark current at low temperatures, by reducing the transition temperature from diffusion-limited to depletion-limited dark current. Another advantage is that the wider bandgap obtained in the vicinity of the junction ensures less sensitivity to the defects present at the interface between MCT and passivation layers. Electro-optical characterization of p-on-n photodiodes was performed on quarter video graphics array format FPAs with 25 and 30 μm pixel pitches. The results revealed excellent operabilities in current and responsivity, with low dispersion, and noise limited by current shot noise. Studies performed on the dark current show that dark current densities at 78 K are consistent with the heuristic prediction law “Rule 07”. Below this temperature, dark current varies as a pure diffusion current for a variety of devices from different manufacturers, introducing a temperature range limitation in the description of the “Rule 07” law.

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines.

Cascade support vector machines (SVMs) are optimized to efficiently handle problems, where the majority of the data belong to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, SVM classification is a computationally demanding task and existing hardware architectures for SVMs only consider monolithic classifiers. This paper proposes the acceleration of cascade SVMs through a hybrid processing hardware architecture optimized for the cascade SVM classification flow, accompanied by a method to reduce the required hardware resources for its implementation, and a method to improve the classification speed utilizing cascade information to further discard data samples. The proposed SVM cascade architecture is implemented on a Spartan-6 field-programmable gate array (FPGA) platform and evaluated for object detection on 800×600 (Super Video Graphics Array) resolution images. The proposed architecture, boosted by a neural network that processes cascade information, achieves a real-time processing rate of 40 frames/s for the benchmark face detection application. Furthermore, the hardware-reduction method results in the utilization of 25% less FPGA custom-logic resources and 20% peak power reduction compared with a baseline implementation.

Commercially applicable, solution-processed organic TFT and its backplane application in electrophoretic displays

We report a video graphics array (VGA) electrophoretic display (EPD) that adopts commercially applicable process technologies for its solution-processed organic thin-film transistor (OTFT). For source/drain (S/D) engineering, a copper (Cu) electrode was employed instead of high-work-function materials and to obtain a low-resistance signal line on the array that is functionalized by self-assembled monolayer (SAM) treatment on the electrode surface. For gate engineering, a gate electrode with Cu was successfully formed onto the organic gate insulator (OGI) by using sputter deposition, thus providing an industrially suitable technology to replace evaporation processes even on frail organic material. Competitive device performance driving the electrophoretic display was obtained on a TFT derived from anthradithiophene that was fabricated at low temperatures of less than 140°C and that has the stable electrical feature of ΔVT of 3V for induced bias stress with a long time span. Up until now, electrode engineering using low-cost and low-work-function materials has been too problematic for practical use of OTFT backplanes, but we have successfully applied it to produce a 6-in. electrophoretic display based on a large substrate of 370×470mm2 for the backplane process. Thus, as far as mass production is concerned, the solution-processed organic transistor shows promise as a backplane unit with low-temperature processing.

Development of an all-in-one gamma camera/CCD system for safeguard verification

For the purpose of monitoring and verifying efforts at safeguarding radioactive materials in various fields, a new all-in-one gamma camera/charged coupled device (CCD) system was developed. This combined system consists of a gamma camera, which gathers energy and position information on gamma-ray sources, and a CCD camera, which identifies the specific location in a monitored area. Therefore, 2-D image information and quantitative information regarding gamma-ray sources can be obtained using fused images. A gamma camera consists of a diverging collimator, a 22 × 22 array CsI(Na) pixelated scintillation crystal with a pixel size of 2 × 2 × 6 mm3 and Hamamatsu H8500 position-sensitive photomultiplier tube (PSPMT). The Basler scA640-70gc CCD camera, which delivers 70 frames per second at video graphics array (VGA) resolution, was employed. Performance testing was performed using a Co-57 point source 30 cm from the detector. The measured spatial resolution and sensitivity were 4.77 mm full width at half maximum (FWHM) and 7.78 cps/MBq, respectively. The energy resolution was 18% at 122 keV. These results demonstrate that the combined system has considerable potential for radiation monitoring.

High dynamic range adaptation for ROI tracking based on reconfigurable concurrent dual‐sensing

A single-exposure technique to extend the dynamic range of vision sensors is presented. It is particularly suitable for vision algorithms requiring region-of-interest (ROI) tracking under varying illumination conditions. The operation is supported by two intertwined photo-diodes at pixel level and two digital registers at the periphery of the pixel matrix. These registers divide the focal plane into independent regions within which automatic concurrent adjustment of the integration time takes place for each frame. At pixel level, one of the photodiodes senses the pixel value itself, whereas the other, in collaboration with its counterparts in every prescribed ROI, senses the mean illumination of that specific ROI. An additional circuitry interconnecting both photodiodes asynchronously determines the integration period for each ROI according to its mean illumination. The experimental results for a quarter video graphics array prototype CMOS vision sensor are reported.

IJARCCE - Computer and Communication Engineering

Surveillance cameras are video cameras used for the purpose of observing an area. Sensitive areas need to be observed continuously for security reasons. The security of these areas shall not be depending on the size of an area but, shall be considered on the high priority of security. Before few decades this task was done by the humans, but now it is not possible for human to keep watch day and night (24x7) on such areas. We all know that there is massive increase in theft in either in one or more ways. Human can easily be distracted and, a small distraction is sufficient for thieves to break the security. System is proposed and presented using our own data set captured in laboratory datasets. The proposed system works on QVGA (Quarter Video Graphics Array) resolution at which most CCTV (closed circuit television) cameras operate and uses a simple mathematical model for detection of human and object. Proposed work is a combination of base works as 1: Real time video feed. 2: Discover frame from the video after fixed time interval. 3: Dual time background subtraction algorithm which periodically updates two sets of background. 4: Deriving a reference image. 5: Maintaining a Buffered Background image/frame. 6: Blob detection. 7: Motion Tracking. 8: Object tracking. 9: Detection and maintaining log of and Alarm signalling. An algorithm for tracking of abandoned objects even under occlusion is also proposed.

Development of 8‐in. oxide‐TFT‐driven flexible AMOLED display using high‐performance red phosphorescent OLED

AbstractAn 8‐in. flexible active‐matrix organic light‐emitting diode (AMOLED) display driven by oxide thin‐film transistors (TFTs) has been developed. In‐Ga‐Zn‐O (IGZO)‐TFTs used as driving devices were fabricated directly on a plastic film at a low temperature below 200 °C. To form a SiOx layer for use as the gate insulator of the TFTs, direct current pulse sputtering was used for the deposition at a low temperature. The fabricated TFT shows a good transfer characteristic and enough carrier mobility to drive OLED displays with Video Graphic Array pixels. A solution‐processable photo‐sensitive polymer was also used as a passivation layer of the TFTs. Furthermore, a high‐performance phosphorescent OLED was developed as a red‐light‐emitting device. Both lower power consumption and longer lifetime were achieved in the OLED, which used an efficient energy transfer from the host material to the guest material in the emission layer. By assembling these technologies, a flexible AMOLED display was fabricated on the plastic film. We obtained a clear and uniform moving color image on the display.

Uncooled infrared detectors toward smaller pixel pitch with newly proposed pixel structure

An uncooled infrared (IR) focal plane array (FPA) with 23.5 μm pixel pitch has been successfully demonstrated and has found wide commercial applications in the areas of thermography, security cameras, and other applications. One of the key issues for uncooled IRFPA technology is to shrink the pixel pitch because the size of the pixel pitch determines the overall size of the FPA, which, in turn, determines the cost of the IR camera products. This paper proposes an innovative pixel structure with a diaphragm and beams placed in different levels to realize an uncooled IRFPA with smaller pixel pitch (≦17 μm ). The upper level consists of a diaphragm with VO x bolometer and IR absorber layers, while the lower level consists of the two beams, which are designed to be placed on the adjacent pixels. The test devices of this pixel design with 12, 15, and 17 μm pitch have been fabricated on the Si read-out integrated circuit (ROIC) of quarter video graphics array (QVGA) (320×240 ) with 23.5 μm pitch. Their performances are nearly equal to those of the IRFPA with 23.5 μm pitch. For example, a noise equivalent temperature difference of 12 μm pixel is 63.1 mK for F/1 optics with the thermal time constant of 14.5 ms. Then, the proposed structure is shown to be effective for the existing IRFPA with 23.5 μm pitch because of the improvements in IR sensitivity. Furthermore, the advanced pixel structure that has the beams composed of two levels are demonstrated to be realizable.

Multichannel Computer Screen Recording System Based on FPGA and ARM

A multichannel computer screen recording system based on Field Programmable Gate Array (FPGA) and Advanced RISC Machines (ARM) is introduced in this paper. This system has both Video Graphics Array (VGA) and Digital Video Interface (DVI) inputs, and supports the resolution of 1920x1080 and any common resolutions that do not exceed 1600x1200. The system can simultaneously record VGA and DVI signal by using the FPGA as the MUX of VGA and DVI. The experimental results showed that the algorithm used in this system, which combined the wavelet transform and listless zerotree entropy coding, achieved significantly higher quality of the decoded images than JPEG with the same compression ratio. The mapping of FPGA to SRAM method ensures the bit stream band width between FPGA and ARM. With the compression ratio of 50, the system can record 20 frames per second at the resolution of 1600x1200.

SoC Implementation of VGA Driver using Spartan 3AN Series FPGA

As the microelectronic industry grows there has been an exponential increase in the importance of FPGAs in modern digital circuit design. FPGAs not only provided an advantage of being reconfigurable but also come in extremely small packaging. In this paper we use the Xilinx Spartan 3AN series FPGA and propose its use as part of a System on Chip controller for a Video Graphics Array (VGA), that serves as one of the most popular display units today.

Computer-assisted orthognathic surgery: waferless maxillary positioning, versatility, and accuracy of an image-guided visualisation display

There may well be a shift towards 3-dimensional orthognathic surgery when virtual surgical planning can be applied clinically. We present a computer-assisted protocol that uses surgical navigation supplemented by an interactive image-guided visualisation display (IGVD) to transfer virtual maxillary planning precisely. The aim of this study was to analyse its accuracy and versatility in vivo. The protocol consists of maxillofacial imaging, diagnosis, planning of virtual treatment, and intraoperative surgical transfer using an IGV display. The advantage of the interactive IGV display is that the virtually planned maxilla and its real position can be completely superimposed during operation through a video graphics array (VGA) camera, thereby augmenting the surgeon's 3-dimensional perception. Sixteen adult class III patients were treated with by bimaxillary osteotomy. Seven hard tissue variables were chosen to compare (ΔT1–T0) the virtual maxillary planning (T0) with the postoperative result (T1) using 3-dimensional cephalometry. Clinically acceptable precision for the surgical planning transfer of the maxilla (<0.35mm) was seen in the anteroposterior and mediolateral angles, and in relation to the skull base (<0.35°), and marginal precision was seen in the orthogonal dimension (<0.64mm). An interactive IGV display complemented surgical navigation, augmented virtual and real-time reality, and provided a precise technique of waferless stereotactic maxillary positioning, which may offer an alternative approach to the use of arbitrary splints and 2-dimensional orthognathic planning.