Very Long Instruction Word Processor Research Articles

Multiple modular very long instruction word processors based on field programmable gate arrays

Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shorten the development cycle and to use the totality of the powerful FPGA resources in order to increase real-time performance. Some common algorithms of image processing and a face tracking in video sequences application were created and validated on an FPGA VirtexII-2000 multimedia board using the development cycle proposed. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with system-level software. This makes our approach suitable for developing co-design environments. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. In this paper, the target VLIW processor is the DSP TMS320C6x. Nonetheless, our design cycle can be generalized to other DSP processors.

Hybrid multi-core architecture for boosting single-threaded performance

The scaling of technology and the diminishing return of complicated uniprocessors have driven the industry towards multicore processors. While multithreaded applications can naturally leverage the enhanced throughput of multi-core processors, a large number of important applications are single-threaded, which cannot automatically harness the potential of multi-core processors. In this paper, we propose a compiler-driven heterogeneous multicore architecture, consisting of tightly-integrated VLIW (Very Long Instruction Word) and superscalar processors on a single chip, to automatically boost the performance of single-threaded applications without compromising the capability to support multithreaded programs. In the proposed multi-core architecture, while the high-performance VLIW core is used to run code segments with high instruction-level parallelism (ILP) extracted by the compiler; the superscalar core can be exploited to deal with the runtime events that are typically difficult for the VLIW core to handle, such as L2 cache misses. Our initial experimental results by running the preexecution thread on the superscalar core to mitigate the L2 cache misses of the main thread on the VLIW core indicate that the proposed VLIW/superscalar multi-core processor can automatically improve the performance of single-threaded general-purpose applications by up to 40.8%.

Optimizing Scalable Video Compression for Efficient Implementation on a VLIW Media Processor

State-of-the-art digital multimedia platforms contain a powerful very-long instruction word (VLIW) processing core. To obtain optimum performance on such a platform, a media-processing algorithm should exploit all the advantages provided by the VLIW processor's architecture. This paper focuses on a method for adapting a video compression algorithm for implementation on a VLIW processor using algorithm-architecture co-design. We demonstrate the importance of our adaptation approach and show the improved efficiency of the algorithm implementation

SIMDE: An educational simulator of ILP architectures with dynamic and static scheduling

AbstractThis article presents SIMDE, a cycle‐by‐cycle simulator to support teaching of Instruction‐Level Parallelism (ILP) architectures. The simulator covers dynamic and static instruction scheduling by using a shared structure for both approaches. Dynamic scheduling is illustrated by means of a simple superscalar processor based on Tomasulo's algorithm. A basic Very Long Instruction Word (VLIW) processor has been designed for static scheduling. The simulator is intended as an aid‐tool for teaching theoretical contents in Computer Architecture and Organization courses. The students are provided with an easy‐to‐use common environment to perform different simulations and comparisons between superscalar and VLIW processors. Furthermore, the simulator has been tested by students in a Computer Architecture course in order to assess its real usefulness. © 2007 Wiley Periodicals, Inc. Comput Appl Eng Educ 14: 226–239, 2007; Published online in Wiley InterScience (www.interscience.wiley.com); DOI 10.1002/cae.20154

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1) a 4-way VLIW processor implemented in an FPGA, (2) large speedups through hardware functions, (3) a hardware/software interface with zero overhead, (4) a design methodology for implementing signal processing applications on this architecture, (5) tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

Real-time Face Recognition Using SIMD and VLIW Architecture

There is a rapidly growing demand for using intelligent cameras for various applications in surveillance and identification. Most of these applications have real-time demands and require huge processing capacity. Face recognition is one of those applications highly in demand. In this paper we show that we can run face recognition in real-time by implementing the algorithm on an architecture which combines a massively parallel processor with a high performance Digital Signal Processor. In this paper we focus on the INCA+ intelligent camera. It contains a CMOS sensor, a Single Instruction Multiple Data (SIMD) processor [1] and a Very Long Instruction Word (VLIW) processor. The SIMD processor enables high-performance pixel processing and detects the interesting (face) regions from the video. It sends the regions of interest to the VLIW processor, which performs the actual face recognition using a neural network. With this architecture we perform face recognition from a 5-persons database at more than 200 faces per second. The performance is better than most recent high-end professional systems [2].

INCORPORATING FAULT-TOLERANT FEATURES IN VLIW PROCESSORS

In recent years, very long instruction word (VLIW) processor has attracted much attention in that it offers a high instruction level parallelism and reduces the hardware design complexity. In this paper, we present two fault-tolerant schemes for VLIW processors. The first one is termed as test-instruction scheme which is based on the concept of instruction duplication to detect the errors. The process of test-instruction scheme consists of the error detection, error rollback recovery and reconfiguration. The second approach is called self-checking scheme which adopts the concept of self-checking logic to detect the errors. A real-time error recovery procedure is developed to conquer the errors. We implement the proposed designs of fault-tolerant VLIW processor in VHDL and employ the fault injection and fault simulation to validate our schemes. The main contribution of this research is to present the complete frameworks from error detection to error recovery for fault-tolerant design of VLIW processors. Experience learned from this investigation is that the issues of error detection and error recovery entail considering together. Without taking both issues into account simultaneously, the outcomes may lead to the improper conclusions.

Reducing the complexity of instruction-level power models for VLIW processors

Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K-issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(?ISA? K ) to quadratic (O(K*?ISA?2)). The complexity of the energy model has been further simplified by automatically clustering the operations in the ISA with respect to their average energy. Globally, the proposed approach reduces the complexity of the characterization problem for a K-issue VLIW processor to quadratic (O(K*?C?2)) with respect to the number of operation clusters. In this way, a more efficient characterization of the VLIW core power consumption can been achieved, while preserving the accuracy of the power estimates. The proposed model has been further extended to provide early power figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of multiple data-path units and a single instruction cache control unit. The proposed high-level power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor provided by STMicroelectronics.

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations, matching the low-power characteristics of the target VLIW processors. Experimental results have been carried out on Lx, an industrial 4-issue VLIW architecture.

Software pipelining

The basic idea behind software pipelining was first developed by Patel and Davidson for scheduling hardware pipe-lines. As instruction-level parallelism made its way into general-purpose computing, it became necessary to automate scheduling. How and whether instructions can be scheduled statically have major ramifications on the design of computer architectures. Rau and Glaeser were the first to use software pipelining in a compiler for a machine with specialized hardware designed to support software pipelining. In the meantime, trace scheduling was touted to be the scheduling technique of choice for VLIW (Very Long Instruction Word) machines. The most important contribution from this paper is to show that software pipelining is effective on VLIW machines without complicated hardware support. Our understanding of software pipelining subsequently deepened with the work of many others. And today, software pipelining is used in all advanced compilers for machines with instruction-level parallelism, none of which, except the Intel Itanium, relies on any specialized support for software pipelining.This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipelining is that optimal performance can be achieved with compact object code.This paper extends previous results of software pipelining in two ways: First, this paper shows that by using an improved algorithm, near-optimal performance can be obtained without specialized hardware. Second, we propose a hierarchical reduction scheme whereby entire control constructs are reduced to an object similar to an operation in a basic block. With this scheme, all innermost loops, including those containing conditional statements, can be software pipelined. It also diminishes the start-up cost of loops with small number of iterations. Hierarchical reduction complements the software pipelining technique, permitting a consistent performance improvement be obtained.The techniques proposed have been validated by an implementation of a compiler for Warp, a systolic array consisting of 10 VLIW processors. This compiler has been used for developing a large number of applications in the areas of image, signal and scientific processing.

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors

Switching activity and schedule length are the two most important factors that influence the energy consumption of an application executed on a VLIW (very long instruction word) processor. Considering these two factors together, we propose an instruction-level energy-minimisation scheduling technique to reduce the energy consumption of applications on VLIW processors. We first formally prove that this problem is NP-complete. Then three heuristic algorithms, MSAS, MLMSA, and EMSA, are proposed. While switching activity and schedule length are given higher priority in MSAS and MLMSA respectively, EMSA gives the best result considering both of them. The experimental results show that EMSA gives a 31.7% reduction in energy compared with the traditional list scheduling approach on average.

A VLIW processor with reconfigurable instruction set for embedded applications

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-μm CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3× to 13.5× and energy consumption reduced up to 92%.

An instruction-level energy model for embedded VLIW architectures

In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a K-issue VLIW processor is O(N/sup 2K/) where N is the number of operations in the ISA and K is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducing the complexity of the characterization problem to O(K/spl times/N/sup 2/). The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline.

적극적인 명령어 압축을 통한 성능향상

본 논문에서는 독립적으로 스케쥴링할 수 있는 VLIW 명령어들을 소개함으로써, 컴파일러와 프로세서에서의 스케줄링 작업을 더욱 균등하게 분배할 수 있는 프로세서 구조를 제안하였다. 제안한 APVLIW(Aggressively Packed VLIW) 프로세서의 목표는 자료종속성을 포함한 VLIW 명령어들을 독립적으로 스케줄링이다. APVLIW 프로세서는 기존의 VLIW 코드로부터 대부분의 NOP(No Operations)과 LNOP(Long NOPs) 명령어들을 제거함으로써 압축된 형태의 긴명령어 그룹을 생성한다. 본 논문에서 제안된 APVLIW 프로세서는 여러 개의 연산처리기와 동적 스케줄러의 쌍들과 자료종속성 정보를 사용하여 긴명령어내의 각 명령어를 독립적으로 스케줄링할 수 있다. 이러한 스케줄링 기법은 특히 루프를 포함한 프로그램을 실행할 때 효과적이다. 실험 결과를 통해서 캐시크기의 변화와 벤치마크 프로그램에 상관없이 APVLIW 프로세서가 VLIM 프로세서에 비하여 성능이 향상됨을 확인하였다. This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing independently scheduled VLIW instructions. Aggressively Packed VLIW (APVLIW) processor is aimed specifically at independent scheduling Very Long Instruction Word(VLIW) instructions with dependency information. The APVLIW processor independently schedules earth instruction within long instructions using functional unit and dynamic scheduler pairs. Every dynamic scheduler dynamically checks far data dependencies and resource collisions while scheduling each instruction. This scheduling is especially effective in applications containing loops. We simulate the architecture and show that the APVLIW processor performs significantly better than the VLIW processor for a wide range of cache sizes and across various numerical benchmark applications.

Very long instruction word processors

The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.

TTAs: Missing the ILP complexity wall

A common approach to enhance the performance of processors is to increase the number of function units which operate concurrently. We observe this development in all recent general purpose superscalar processors, and in VLIW (very long instruction word) processors used for more dedicated application domains, like the multi-media domain. This paper analyzes the data path complexity of ILP processors (in particular VLIWs), and shows that they soon may hit the complexity wall; their complexity gets out of control when scaling to very high performance. Several methods are investigated for reducing this complexity. Essentially these methods trade hardware for software complexity, i.e., performing as much as possible at compile time. Combining these methods results in a new architecture, called transport triggered architecture or TTA. The concept of transport triggering is outlined together with its characteristics. It will be shown that the application of this concept results in a number of hardware advantages, and introduces a number of new scheduling optimizations. Together they substantially reduce the ILP complexity bottleneck, which will be demonstrated by a number of experiments.

DIVA: dual-issue VLIW architecture with media instructions for image processing

According to the demand on enormous multimedia data processing, we have designed a VLIW (very long instruction word) processor called DIVA (dual-issue VLIW architecture) exploiting the ILP (instruction-level parallelism) in multimedia programs. The DIVA processor which can execute two instructions in one cycle supports 86 instructions including 30 media instructions, and has a sub-word execution structure that supports the saturation mode arithmetic for image processing. Compared to scalar architectures without media instructions, the performance of the DIVA processor is improved by 2.2 to 5 times due to the combination of the VLIW architecture and media instructions. The DIVA processor, consisting of about 90,000 gates, was implemented using the 0.6 /spl mu/m CMOS SOG (sea-of-gate) process on a 8 mm/spl times/8 mm die, and has shown a performance of 80 MOPS (million operations per second) at 10 MHz clock frequency.

Simulation/evaluation environment for a VLIW processor architecture

We describe the environment used for the simulation and evaluation of a processor architecture based on very long instruction word (VLIW) principles. In this architecture, a program consists of a set of tree instructions, each one containing multiple branches and operations which can be performed simultaneously. The simulation/evaluation environment comprises • An optimizing compiler, which generates tree instructions in a VLIW assembly language. • A translator from VLIW assembly code into PowerPC® assembly code which emulates the functionality of the VLIW processor for the specific VLIW program. The emulating code also includes instrumentation for collecting execution counts of VLIWs, profiling information, and generation of predecoded execution traces. • A cycle timer, invoked by the emulating code on a VLIW-by-VLIW basis, which processes VLIW execution traces as they are generated. The environment supports the evaluation of alternatives and trade-offs among the VLIW architecture, its compiler, and processor implementations. Emphasis has been placed on providing fast turnaround time for the development of compilation algorithms and an efficient compilation-to-simulation cycle which allows analysis of architecture/compiler trade-offs over complete execution runs of realistic workloads.

Trace software pipelining

Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Trace Software Pipelining, targeted to the instruction-level parallel processors such as Very Long Instruction Word (VLIW) and superscalar machines. Trace software pipelining applies a global code scheduling technique to compact the original loop body. The resulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or can be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promising in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.

Pipelining and bypassing in a VLIW processor

This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor. The authors first describe the pipeline structure of their processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next they study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time. >