Vertical Pin Research Articles

Breakdown characteristics analysis of kV-class vertical GaN PIN rectifiers by wafer-level sub-bandgap photoluminescence mapping

Breakdown characteristics analysis of kV-class vertical GaN PIN rectifiers by wafer-level sub-bandgap photoluminescence mapping

Vertical GaN PIN Structure with Intrinsic AlGaN Drift Layer Grown Using Metal‐Organic Chemical Vapor Deposition

In this study, it is aimed to examine the DC characteristics of a vertical PIN diode featuring AlGaN as the drift layers. In the investigation, observing the changes in DC characteristics with the variation of Al content (0%–4%) in the drift layers as well as its thickness is focused on. By applying AlGaN as the drift layer, the semi‐insulating properties are augmented and the detrimental background carbon impurity is reduced, leading to a reduction in the leakage current and an improvement in the breakdown voltage characteristics of the device. Room‐temperature and low‐temperature photoluminescence measurements confirm a reduction in the intensity of both yellow luminescence and blue luminescence, which can be attributed to the decrease in defect concentration. Furthermore, to minimize the occurrence of premature breakdown voltage, p‐type GaN is meticulously etched into a bevel shape, and subsequent confirmation through the utilization of a scanning electron microscope reveals an inclination of 13°. The outcome of the analysis on the DC characteristic indicates an improvement in reverse‐bias characteristics with the increase in the Al ratio in the drift layer for the 2 μm series. Furthermore, for the 20 μm Al0.04Ga0.96N, a breakdown voltage of 2540 V is recorded.

Extended short-wave infrared high-speed all-GeSn PIN photodetectors on silicon

There is an increasing need for silicon-compatible high-bandwidth extended-short wave infrared (e-SWIR) photodetectors (PDs) to implement cost-effective and scalable optoelectronic devices. These systems are quintessential to address several technological bottlenecks in detection and ranging, surveillance, ultrafast spectroscopy, and imaging. In fact, current e-SWIR high-bandwidth PDs are predominantly made of III–V compound semiconductors and thus are costly and suffer a limited integration on silicon besides a low responsivity at wavelengths exceeding 2.3 μm. To circumvent these challenges, Ge1−xSnx semiconductors have been proposed as building blocks for silicon-integrated high-speed e-SWIR devices. Herein, this study demonstrates vertical all-GeSn PIN PDs consisting of p-Ge0.92Sn0.08/i-Ge0.91Sn0.09/n-Ge0.89Sn0.11 and p-Ge0.91Sn0.09/i-Ge0.88Sn0.12/n-Ge0.87Sn0.13 heterostructures grown on silicon following a step-graded temperature-controlled epitaxy protocol. The performance of these PDs was investigated as a function of the device diameter in the 10–30 μm range. The developed PD devices yield a high bandwidth of 12.4 GHz at a bias of 5 V for a device diameter of 10 μm. Moreover, these devices show a high responsivity of 0.24 A/W, a low noise, and a 2.8 μm cutoff wavelength, thus covering the whole e-SWIR range.

Single-event burnout in homojunction GaN vertical PiN diodes with hybrid edge termination design

GaN devices play a major role in modern electronics, providing high-power handling, efficient high-frequency operation, and resilience in harsh environments. However, electric field crowding at the edge of the anode often limits its full potential, leading to single-event effects (SEEs) at lower bias voltages under heavy ion radiation. Here, we report on the performance of homojunction GaN vertical PiN diodes with a hybrid edge termination design under heavy ion irradiation, specifically, oxygen ions, chlorine ions, Cf-252 fission fragments, and alpha particles from an Am-241 source. The unique hybrid edge termination (HET) design provides better electric field management, preventing breakdown from occurring at the edge of the anode at lower voltages. The results of this study reveal that these devices exhibit excellent tolerance to 12-MeV oxygen and 16-MeV chlorine ions, owing to their low linear energy transfer (LET) and range in GaN. However, single-event burnout (SEB) is observed during the Cf-252 exposure at about 50% of the diodes' electrical breakdown voltage due to the presence of higher LET and longer-range ions. Optical and scanning electron microscopy (SEM) reveal that the damage that caused by SEB lies close to the center of these devices rather than the anode edge. Devices with junction termination extension (JTE) instead of HET edge termination also show similar SEB when irradiated with Cf-252 fission fragments. Physical damage due to SEB occurs at the edge of the anode for these devices. These comparative results show the benefits of HET for enhancing the resistance of GaN-based PiN diodes to heavy ion irradiation.

High-uniformity and high-performance waveguide Ge photodetectors for the O and C bands.

This paper presents the test results for high-performance and high-uniformity waveguide silicon-based germanium (Ge) photodetectors (PDs) for the O band and C band. Both wafer-scale and chip-scale test results are provided. The fabricated lateral p-i-n (LPIN) PDs exhibit a responsivity of 0.97A/W at a bias of -2V, a bandwidth of 60GHz, and a no-return-to-zero (NRZ) eye diagram rate of 53.125Gb/s. Additionally, an average dark current of 22.4nA was obtained in the vertical p-i-n (VPIN) PDs at -2V by optimizing the doping process. The device can reach an average responsivity of 0.9A/W in the O band. The standard deviation in a wafer with a dark current and responsivity is as low as 7.77nA and 0.03A/W at -2V, respectively.

Instability of On-Resistance in Vertical GaN PIN Diodes Under High-Temperature and Voltage Stress

Instability of On-Resistance in Vertical GaN PIN Diodes Under High-Temperature and Voltage Stress

Self-powered 4 H-SiC charged particle detector with 1 cm2 sensitive area and 0.63% energy resolution

Silicon carbide (SiC) detector, one of important charged particle detectors with good endurance in high-temperature and harsh-radiation environment, is highly demanded for high energy resolution and large sensitive area, but is hardly to acquire for decades. In this paper, a SiC charged particle detector was fabricated using high-quality homogenous epitaxial 4 H-SiC wafer with thickness of 150 μm and in vertical PIN diode structure; high-performance of low dark current (0.60 nA/cm2 within reverse bias of 600 V), large sensitive area (1 cm2) and high energy resolution (0.63%) were successfully achieved; furthermore, the detector was proven as self-powered charged particle detector for high charge collection efficiency of 95.96% and proper energy resolution at a bias voltage of 0 V. We envision that SiC charged particle detector would promote further development of radiation detection and charged particle spectrometer.

A Comparative Study of Flow Boiling Heat Transfer and Pressure Drop Characteristics in a Pin-Finned Heat Sink at Horizontal/Vertical Upward Flow Orientations

Abstract With the continuous development of power electronic devices toward miniaturization and compactness, it is necessary to develop more efficient flow boiling heat transfer technologies. In this work, the flow boiling heat transfer and pressure drop characteristics of Novec649 in a pin finned channel under two kinds of flow orientations (horizontal and vertical upward) are experimentally investigated. Heat flux, inlet flow velocity, and inlet subcooling are considered as the variable parameters. The results show that among all boiling operating conditions, the heat transfer performances between two orientations are basically consistent, while the pressure drop of vertical upward pin finned channel is relatively lower, indicating that the comprehensive flow boiling heat transfer performance of vertical oriented channel is better. Subsequently, a series of flow visualization experiments are performed in vertical upward pin finned channel. With the increase of heat flux, four kinds of flow pattern are discovered in the order of dispersed bubble flow, bubble flow, homogeneous flow, and annular flow. In the region of annular flow, although a vapor flow has already formed in the channel, there is still a large amount of liquid phase surrounding the wall and pin fins. Therefore, no obvious heat transfer deterioration was observed in the pin finned channel. Along the flow direction, the diameter of bubbles will increase first, and then present obvious oscillation. As the heat flux increases, both the average bubble detachment diameter and the frequency increase correspondingly. As the fluid velocity increases, the average bubble detachment diameter presents a downward trend, while the average bubble detachment frequency presents an upward trend.

Study of anode doping and avalanche in foundry compatible 1.2 kV vertical GaN PiN diodes

Foundry compatible vertical GaN PiN diodes were fabricated. The devices investigated in this work are based on 8 um drift layer thickness to achieve ∼1.2 kV of voltage blocking. Three different anode doping levels were fabricated on three wafers with the same p-layer thickness, and planar hybrid edge termination. The moderate anode doping level of 1 × 1018 cm−3 has achieved the highest breakdown voltage of 1.2 kV and its temperature-dependent breakdown behavior proved an avalanche behavior. Furthermore, our electroluminescence displayed the breakdown at the edge of the anode. Our simulation results imply an improvement in the field management with moderate anode doping.

Configuration of the active region for the Ge-on-Si photodetector based on carrier mobility

The design of vertical and lateral PIN Ge-on-Si photodetectors was motivated by the disparity in electron and hole mobilities. In the case of vertical PIN junction detectors, configuring the slab region as n-type doping leads to a notable increase in the bandwidth of approximately 20 GHz compared to utilizing p-type doping for the slab. For lateral PIN junction detectors, we determined that setting the length of the n-type slab region to be 2.8 times that of the p-type slab region, based on the carrier saturation drift rate ratio, does not compromise the bandwidth. This configuration enhances the bandwidth while minimizing light absorption loss from the electrode. The proposed design in this study enhances the performance of Ge-on-Si photodetectors without adding complexity to the fabrication process. The principles applied in this study serve as instructive references for the conceptualization of other photonic or electronic devices, reinforcing the widespread applicability of these design strategies.

Ultra-Low Capacitance Spot PIN Photodiodes

Spot PIN photodiodes were integrated without any process modifications in a high-voltage 0.18 μm CMOS technology. These photodiodes are a combination of vertical and lateral PIN photodiodes using the P+ bulk wafer and a P-type ring at the surface as anodes. Devices with N+ cathode and N+/N-well cathode are compared. A small N+/N-well cathode spot reduces the capacitance to 1.47 fF and the N+ cathode spot leads to a capacitance of 1.07 fF. The light sensitive area of these photodiodes is 707 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Simulated electric field distributions show the full depletion of the spot PIN photodiodes. Responsivities from 0.12 A/W to 0.16 A/W and from 0.50 A/W to 0.52 A/W for 405 nm and 675 nm, respectively, are achieved. The measured bandwidths for 675 nm light are from 520 MHz to 690 MHz at reverse biases from 15 V to 30 V.

Robust Si/Ge heterostructure metasurfaces as building blocks for wavelength-selective photodetectors

We present a design for silicon-compatible vertical Germanium pin photodiodes structured into all-dielectric metasurfaces. Proof-of-principle metasurfaces are fabricated on silicon-on-insulator wafers in a top-down process. Simulations and measurements of the spectroscopic properties, specifically the absorption, show high spectral selectivity, and absorption efficiencies as large as those in bulk Germanium layers with about four times the Ge layer thicknesses. Our metasurface structures can be tuned to the target wavelength through tailoring of the lateral geometry. Possible applications include spectroscopy and hyperspectral imaging, with several metasurfaces for different wavelength ranges integrated with readout circuitry into a low-cost electronic–photonic integrated circuit.

Using machine learning with optical profilometry for GaN wafer screening

To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology

During the last decade optical sensor technologies have attracted increased attention for various applications. Plasmon-based optical sensor concepts for the detection of refractive index changes that rely on propagating surface-plasmon polaritons at metal-dielectric interfaces or on localized plasmons in metallic nanostructures prove their potential for these application due to their fast detection speed, high specificity and sensitivities [1, 2]. Combining plasmonic structures directly with optoelectronic devices could enable a high level of integration, however, it represents a significant technological challenge to develop an on-chip solution for these concepts including the integration of sensor and detector components. Previous works demonstrated first approaches mainly for the integration of refractive index sensor components on wafer level [3, 4]. In [5] and [6] a proof-of-concept of a fully integrated on-chip solution with high sensitivities was presented, which can be easily combined with microfluidics [7] for potential applications in biosensing. In this concept, a nanohole array (NHA) was structured in a 100 nm thick aluminum layer on top of a vertical PIN germanium photodetector (GePD) with an intrinsic germanium sheet of 480 nm. This sensor concept relies on extraordinary optical transmission through the NHA [8]: Light transmission is only possible for narrow wavelength ranges determined by the NHA geometry which determine the transmission peaks at the resonance wavelength of the NHA. Thus, the NHA acts as a high quality wavelength filter. Due to the change in the refractive index, a material under test (MUT) contacting directly the surface of the NHA, provokes a shift of the wavelength maximum, which can be detected by measuring the photocurrent spectra of the GePD. While responsivities and sensitivities of (0 V) = 0.075 A/W and = 1200 nm/RIU could be attained in this proof-of-concept device [6, 7], the semiconductor device layers were deposited using molecular beam epitaxy (MBE). Furthermore the vertical PIN GePD was realized by a mesa procedure to enable large areas for top illuminated operations. These techniques are unsuitable for an industrial CMOS fabrication process with high throughput. Therefore, the development of a CMOS compatible technology process with low costs and high yields is an important step towards large-scale fabrication of this sensor concept.In this work we present the progress for the realization of a surface plasmon resonance (SPR) refractive index sensor in a 200 mm wafer Silicon based technology. One main challenge is the fabrication of a large area photodetector for top illuminated sensor devices. We developed a process, which is mainly based on the IHP electronic photonic integrated circuits (ePIC) technology [9]. This ePIC technology enables the production of waveguide coupled lateral PIN GePDs with high bandwidth and high responsivities [10]. However, these PDs are unsuitable for top illuminated applications because of their small germanium areas. Due to certain process conditions with respect to chemical mechanical polishing procedures there are limits for feasible large detector areas. Furthermore, large detector areas for lateral PIN GePDs would result in very low electric fields in the intrinsic zone where carriers are generated by photon absorption. Thus, very high voltages for reversed bias are necessary for sufficient carrier drifts.For the first time we have developed a modern detector design concept which is compatible to the IHP ePIC technology. This concept allows the realization of large area detectors of 1600µm² (40µm x 40µm) with optimized optical responsivities for top illuminated applications. The detector consists of several parallel connected lateral PIN GePDs. We designed different variations and varied Ge width and distance between neighboring GePDs in order to investigate process limits. The p- and n-doped regions were defined by dopant implantation using a photo resist mask. We used a finger-like design as implantation masks to enable one contact area for each p-doped and each n-doped region (Fig. 1). This contacting approach differs from the standard GePD offered in the IHP ePIC technology. We analyzed I-V characteristics in dependence of detector design and contacting scheme (Fig. 2). In addition, process adjustments for the optimization of the germanium quality were investigated to reduce dark currents and to improve optical responsivities (Fig.3).Titanium nitride (TiN) is very promising metallic alloy with respect to thickness homogeneity and low surface roughness. Therefore we used titanium nitride which was deposited by a sputtering process to develop plasmonic active NHA layers. Various process development runs were done to evaluate the NHA performance. Ellipsometry and atomic force microscope measurements were performed to characterize the quality of the TiN layer (Fig.4). Figure 1

A Near-Infrared pin Photodetector of Strain-Enhanced Ge Layer Epitaxially Grown on a Bonded Si-on-Quartz Wafer

In Si photonics, photodetectors (PDs) of a Ge epitaxial layer on Si have been widely used, which show a high photodetection efficiency, or a high responsivity in the O (1.260–1.360 µm) and C (1.530–1.565 µm) bands. However, an issue lies in a low responsivity in the longer wavelength range of L band (1.565–1.625 µm). In this regard, we have proposed a method using a Ge layer epitaxially grown on a Si-on-quartz (SOQ) wafer [1]. The tensile in-plane lattice strain, derived from the thermal expansion mismatch between the Ge layer and base substrate, is enhanced more than 0.3% in Ge on SOQ, despite ~0.2% on Si (or Si-on-insulator). The enhanced strain in Ge on SOQ extends the fundamental optical absorption edge to about 1.65 µm, leading to a potential increase in the L-band responsivity. In this study, a vertical pin PD is fabricated using a Ge layer on SOQ, showing an increased responsivity in the L band.A bonded SQQ wafer was used as the starting substrate, fabricated by Shin-Etsu Chemical Co. Ltd. The top Si (001) layer was 200 nm in thickness, and was heavily doped p-type by B implantation. An undoped Ge epitaxial layer (500 nm) was grown by chemical vapor deposition using GeH4 as the source gas, followed by a growth of Si cap layer (50 nm) using Si2H6. In the top region of Ge layer as well as in the Si cap layer, a heavily n-type doping was carried out by P implantation, forming a vertical pin junction. Finally, a Ti/TiN electrode was formed. Responsivity spectra were measured in the wavelength range of 1.46–1.64 µm at a normal incidence. A reference pin PD was also fabricated using a Ge layer on a standard bulk Si wafer. According to x-ray diffraction measurements, the Ge layer on SOQ showed a tensile strain of 0.33%, despite 0.14% for the reference Ge on Si.Figure 1(a) shows typical current–voltage curves for a pin diode of Ge on SOQ measured under dark and under an illumination of 1.55-µm light (1.1 mW). The diode showed a good rectifying property under dark, while under the illumination, the current in the reverse bias significantly increased, showing a reasonable PD operation. Figure 1(b) shows typical responsivity spectra at a reverse bias of 1 V for PDs of Ge on SOQ and reference Ge on Si. Circles and lines correspond to experimental data points and theoretical curves, respectively. The responsivity for Ge on SOQ was larger in the measured wavelength range of 1.46–1.64 µm, including the L band. The increased responsivity is ascribed to the enhanced tensile strain. However, the increase in the L band was found to be suppressed by a high reflectance because of the multiple reflections at the interfaces. An optimized Si cap thickness as well as an anti-reflection coating with SiO2 can increase the normal-incidence responsivity as high as 0.3 (0.1) A/W up to 1.60 (1.64) µm without an increase in the Ge thickness.[1] Noguchi et al., J. Appl. Phys. 128, 133107 (2020). Figure 1

Investigation of the Reverse Leakage Behavior and Substrate Defects in Vertical GaN Schottky and PIN Diodes

In this work, the effects of the substrate defect density and distribution on the reverse leakage behavior of GaN vertical Schottky diodes and p–i–n diodes are investigated. A direct connection between the reverse leakage behavior of GaN based vertical devices and the dislocation density of the underlying material was determined. The difference in the leakage current for devices on different locations of the wafer can be as high as 6 orders of magnitude (for p–i–n diodes) at −200V, for HVPE substrate with inhomogeneous but predictable defect distributions (GaN substrates with dot-core inversion domain features). For comparison, using HVPE substrates with uniform defect distribution (but with no cores), the p–i–n diodes show much more uniform leakage behavior, varying within only an order of magnitude, and that range fell within the much greater range of that for the inhomogeneous substrates. The substrates with inhomogeneous defect distribution proved to be useful to show the direct correlation. The topography measurements confirmed that the wafers with inhomogeneous defect distribution possess periodically patterned core-centers with higher defect density and larger lattice distortions surrounded by other regions, which have very low defect concentrations. Devices located away from the defective core-centers result in a reduction of the reverse bias leakage by over two orders of magnitude at −10 V for Schottky diodes. Similar trends are also observed in the p–i–n diodes; the devices close to the core centers show the highest reverse leakage (>0.01 A cm−2 at −200V). Devices further away from the core-centers (lower dislocation density) show lower reverse leakage current. Moreover, the p–i–n diodes on regions more than 300 μm away from the core-centers show the best leakage behavior (<10−7 A cm−2 at −200V) of all the devices, outperforming the devices on the substrates with uniform defect distribution (∼10−6 A cm−2 at −200V). The results from this study show that the substrate defect density and distribution play important roles in the device leakage current. X-ray topography is extremely effective for studying defect characteristics underneath individual devices. The use of the wafers with inhomogeneous, but predictable defect density clearly demonstrated the importance of low defect densities for high device performance.

Impact of Anode Thickness on Breakdown Mechanisms in Vertical GaN PiN Diodes with Planar Edge Termination

GaN vertical PiN diodes with different anode thicknesses were fabricated on three native GaN wafers with the same p-layer doping concentrations, and planar hybrid edge termination. The breakdown behavior in terms of the breakdown voltage and the electroluminescence were studied as functions of the anode thickness. A repeatable avalanche breakdown and highest breakdown voltage were measured with the thinnest anode of 300 nm and with the thinnest edge termination region. This indicates the efficacy of the nitrogen-implanted hybrid edge termination design that comprises of junction termination and guard rings hybrid design. As the anode thickness increases, the edge termination thickness increases, and the devices exhibit lower breakdown voltages and less robust breakdown characteristics, often destructive. From this study, we also conclude that a very high p-layer doping of 2 × 1019 cm−3 is not s practical doping level, because it is too sensitive to the edge termination thickness.

Low-frequency noise characteristics of GaN vertical PIN diodes—Effects of design, current, and temperature

We report low-frequency noise characteristics of vertical GaN PIN diodes, focusing on the effects of the diode design, current, and temperature. The as-grown and regrown diodes, with and without surface treatment, have been studied. The noise in most of the GaN devices had a characteristic 1/f spectrum at high and moderate currents, while some devices revealed generation-recombination bulges at low currents (f is the frequency). The predominant trend of the noise spectral density, SI, dependence on the current was SI ∼ I. All tested GaN PIN diodes had rather low normalized noise spectral densities of 10−18–10−16 cm2/Hz (f = 10 Hz) at the current density J = 1 A/cm2 at room temperature. The noise temperature dependences at different currents revealed peaks at T = 375–400 K. Temperature, current, and frequency dependences of noise suggest that the noise mechanism is of the recombination origin. We argue that the noise measurements at low currents can be used to efficiently assess the quality of GaN PIN diodes.

Heat transfer characterization under radial jet and falling film induced rewetting

Abstract Empirical correlations are developed for rewetting velocity and maximum heat transfer coefficient during rewetting phase of single hot vertical Fuel Pin Simulator (FPS) by using radial jet impingement and falling film. Emergency Core Cooling System (ECCS) has been designed for Advance Heavy water Reactor (AHWR) to rewet the hot fuel pin under the loss of coolant accident. Coolant injection takes place from a water rod which is located at the center of the fuel bundle in form of jets to rewet hot surface of fuel pin under loss of coolant accident. This kind of design to reflood the fuel bundle is different than bottom and top spray reflooding practiced in PWR and BWR type of nuclear reactors. There are two different kinds of rewetting found during radial jet induced cooling. The first one is due to radial jet impingement and the second one is due to falling film which is below the jet impingement point. Rewetting velocity has been predicted along the length of fuel pin due to radial jet impingement cooling. Temperature of FPS has been varied from 400°C to 700°C with help of different powers supply, simulating decay heat of reactor. A variation of coolant radial jet mass flow rate is from 0.5 lpm to 1.8 lpm. It is considered during ECCS injection. It has been observed from the experiments that rewetting velocity decreases with increasing the clad surface temperature and increases with increasing the coolant mass flow rate. The rewetting velocity in falling film is found to be nearly 1.8 times higher than rewetting velocity predicted in circumferential direction. Further, it is found that maximum heat transfer coefficient increases with increasing the radial jet coolant mass flow rate. The maximum heat transfer coefficient in case of radial jet impingement is found to be nearly 1.5 times the falling film rewetting. Developed correlation predicts the maximum heat transfer coefficient with experimental data well within the error band of ±10%.

Using Wafer Scale Optical Profilometry to Estimate the Failure Rate of Vertical Pin GaN Diodes

GaN research is important to the development of next generation power conversion technology, for SiC based devices are limited to 13 kV loads, while GaN could theoretically handle 20 kV. Presently, commercialized GaN technology using lateral High Mobility Electron Transistors (HEMTs); however, vertical GaN devices could have 3 times larger critical electric field and a five order of magnitude lower dislocation density. Current GaN substrate manufacturing technology is known to produce inconsistent quality with a varying concentration of defects. These defects are known to cause catastrophic device failure, thus there is motive to develop quick, non-destructive techniques to predict the quality of the wafer before undergoing the expensive fabrication process. Our previous research [1,2], has studied several techniques to predict the quality of devices, and has correlated device quality to Raman spectroscopy data. This talk focuses on using optical profilometry data.Optical profilometry is a non-destructive technique capable of mapping the surface morphology of a whole wafer in a few hours. Since defects in the thin film or epitaxial layer often manifest themselves as abnormalities on the surface, this technique can be used to determine the regions of the sample where devices will fail. Dividing the samples into sub-regions, a generalized extreme studentized deviant test can be used to detect where outliers, which are likely defects, occur. From this, the location of the defects can be mapped and the probability of a devices landing on a defect can be calculated. Additionally, by knowing the location of the defects, they can be avoided thus increasing the device yield.This work was supported by the Office of Naval Research and ARPA-E OPEN+ Kilovolt Devices Cohort directed by Isik Kizilyalli.[1] J.C. Gallagher, T.J. Anderson, A.D. Koehler, M.A. Ebrish, G.M. Foster, M.A. Mastro, J.K. Hite, B.P. Gunning, R.J. Kaplar, K.D. Hobart, F.J. Kub, Effect of GaN Substrate Properties on Vertical GaN PiN Diode Electrical Performance, J. Electron. Mater. (2021). doi:10.1007/s11664-021-08840-9.[2] J.C. Gallagher, T.J. Anderson, L.E. Luna, A.D. Koehler, J.K. Hite, N.A. Mahadik, K.D. Hobart, F.J. Kub, Long range, non-destructive characterization of GaN substrates for power devices, J. Cryst. Growth. 506 (2019) 178–184. doi:10.1016/j.jcrysgro.2018.10.032.