Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor Research Articles

Dual‐Stepped Gate Vertical Double‐Diffused Metal‐Oxide‐Semiconductor Field‐Effect Transistor with Enhanced Device Performance

Herein, vertical double‐diffused metal‐oxide‐semiconductor field‐effect transistor(VDMOS) with improved device structure is proposed. Gate engineering is applied in the proposed device and two devices namely dual‐stepped gate technology (DSGT) and modified dual‐stepped gate technology (m‐DSGT) are proposed here. Due to the effect of gate engineering, switching ability is improved and area specific on‐resistance is reduced. Devices are simulated using Silvaco Atlas software. Breakdown voltages for conventional and m‐DSGT are 278.63 and 280.02 V, respectively, for = 0 V. The current density of conventional and m‐DSGT devices is and under the conditions on gate‐driven voltage of 1 V for = 10 V. Using 2D numerical simulations, the electrical performance of both DSGT and m‐DSGT devices is examined. The results demonstrate 76.6% decrease in specific on‐resistance, 4.22 times increase in current density, and 26.67% faster switching speed compared to conventional VDMOS, thus, improving the device performance.

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Charge deposition analysis of heavy-ion-induced single-event burnout in low-voltage power VDMOSFET

The heavy-ion-induced single-event burnout (SEB) risk in power MOSFETs (metal-oxide-semiconductor field-effect transistors) can be assessed in ground facilities, although it is costly and time-demanding. For this reason, there have been few experimental studies dedicated to investigate the relevant parameter related to the description of ion-induced SEB phenomenon. In this work the heavy-ion-induced SEB in a low-voltage power VDMOSFET (vertical double-diffused MOSFET) is studied using several ion-energy combinations. A self-consistent statistical analysis is carried out in order to elucidate the relationship between charge deposition and SEB triggering. Experimental data is compared to a predictive model from the literature for SEE (single-event effect) worst-case prediction in power MOSFETs, supporting for the first time its relevance to the worst-case prediction in the SEB mechanism.

Commercial P-Channel Power VDMOSFET as X-ray Dosimeter

The possibility of using commercial p-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) as X-ray sensors is investigated in this case study. In this aspect, the dependence of sensitivity on both the gate voltage and the mean energy for three X-ray beams is examined. The eight gate voltages from 0 to 21 V are applied, and the dependence of the sensitivity on the gate voltage is well fitted using the proposed equation. Regarding X-ray energy, the sensitivity first increases and then decreases as a consequence of the behavior of the mass energy-absorption coefficients and is the largest for RQR8 beam. As the mass energy-absorption coefficients of SiO2 are not found in the literature, the mass energy-absorption coefficients of silicon are used. The behavior of irradiated transistors during annealing at room temperature without gate polarization is also considered.

Determination of Power MOSFET’s Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes

In this article, we aim to investigate the gate oxide degradation of power MOSFETs through oxide capacitance. We focus on modeling the oxide capacitance variation as a function of several stress levels and time intervals. The experimental procedure is carried out by means of commercial n-channel vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOSFETs) that have maximum voltage and current ratings as 200 V and 5.2A, respectively. We calculate the oxide capacitance using measurable reverse capacitance that is equal to gate–drain capacitance. The turn-around point is determined at each stress level. We observe that the oxide capacitance shows a nonlinear variation due to the stress time and level. The variation is divided into two regions for the model. The modeling procedure starts with the mathematical fitting. The equations are obtained by using curve fitting methods. The circuit model is designed via SPICE Simulation by using these equations. We also consider the turn-around points for the circuit design. The simulation and experimental results have good compatibility. We achieve 92.3% and 90.8% similarity on average for first and second region of the variation, respectively.

Investigating the Failure Mechanism of Short-Circuit Tests in 1.2-kV SiC JBS-Integrated MOSFETs

In this article, the failure mechanism of a 1.2-kV monolithic junction barrier-controlled Schottky diode integrated silicon carbide metal–oxide–semiconductor field-effect transistor (JMOS) under short-circuit (SC) tests has been investigated by an experimental validation and simulation analysis. As a new type of device, JMOS has superior performance and chip area efficiency. However, the SC ruggedness of the JMOS needs further investigation. When comparing vertical double-diffused metal–oxide–semiconductor field-effect transistor (VDMOS) and JMOS devices in the SC test study, the leakage current of the JMOS is much higher than that of a common VDMOS. During the SC test, the JMOS drain current cannot be successfully suppressed after gate turn-off, and the thermionic emission current due to heat generation in the Schottky barrier diode (SBD) region continues flowing into the n-drift region. The SBD thermionic emission current is rapidly increased by the increasing lattice temperature, which can reach over 1600 K. Eventually, the JMOS undergoes thermal runaway due to positive electrothermal feedback. A mechanistic study was set up to analyze the relationship between the SC limit and the leakage current in the SBD region of the heated materials. Finally, the key to improve the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.

Degradation of Radiation-Hardened Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor During Gamma Ray Irradiation Performed After Heavy Ion Striking

The combined impact of single event effect (SEE) and total ion dose (TID) on Si-based radiation-hardened Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) Field-Effect Transistor (VDMO-SFET) is investigated in this letter. As previous research of VDMOS on TID effect and SEE carried out separately, in fact, the combined impact could degrade the device performance more seriously, because of the greater numbers of oxide-trapped charges and interface states generated, which is more pronounced during multiple gamma irradiation and post-irradiation annealing. This phenomenon indicates that SEE is not only a transient effect, influencing whether the devices can be driven to failure, but also a potential threat to the long-term reliability of MOSFETs used in aerospace applications.

Novel Power MOSFET With Partial SiC/Si Heterojunction to Improve Breakdown Voltage by Breakdown Point Transfer (BPT) Terminal Technology

In this paper, a new vertical double-diffused metal-oxide semiconductor field effect transistors (VDMOS) is proposed with the partial SiC/Si heterojunction (Partial SiC/Si VDMOS) under the drain electrode in this paper for the first time. The breakdown point transfer technique (BPT) is used to transfer the breakdown point from the radius of curvature is large to the radius of curvature is small in the interface between Pwell and Ndrift region, which causes the longitudinal peak value of electric field to be raised, and the higher breakdown voltage (BV) can be obtained. At the same time, the formation of highly doped N-type silicon trench alleviates interface state problems caused by current flowing through SiC/Si heterojunction and further optimized the whole SiC/Si heterojunction (SiC/Si VDMOS). The limit line of the silicon has been broken because the result is improved between the BV and the specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). Compared with the conventional Si VDMOS, the BV is increased from 238V to 342V, and the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is reduced from 14.24mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 13.92mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

High electric field stress model of n-channel VDMOSFET based on artificial neural network

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

A review of pulsed NBTI in P-channel power VDMOSFETs

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide-semiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Physico-chemical processes in Vertical-Double-Diffused Metal-Oxide-Semiconductor Field Effect Transistors induced by gamma-ray irradiation and post-irradiation annealing

The behavior of commercial power Vertical-Double-Diffused Metal Oxide Semiconductor Field Effect Transistors (VDMOSFETs) during gamma-ray irradiation and subsequent annealing at room and elevated temperature was investigated. The densities of radiation-induced fixed traps and switching traps were determined from the sub-threshold I-V curves using the midgap technique. It was shown that the creation of fixed traps dominated during irradiation. The experimental results have also proved the existence of latent switching traps buildup process during annealing at an elevated temperature. This increase correlated with the decrease in fixed trap density. Physical and chemical processes responsible for the threshold voltage shift during irradiation have been analyzed on the basis of interactions between secondary electrons released by gamma photons with covalent bonds Sio - O and Sio - Sio. H-W model has been used for the explanation of processes leading to latent switching traps buildup at an elevated temperature and its passivation at late annealing times.

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

PurposeThe purpose of this paper is to apply a negative gate bias stress in order to study instabilities of threshold voltage in N‐channel power vertical double‐diffused metal‐oxide‐semiconductor field effect transistor (VDMOSFET). Variations in gate oxide trapped charge and interface trap densities are also calculated.Design/methodology/approachA threshold voltage shift is detected; the oxide and interface trap densities were evaluated based on a direct measurement of the gate to source capacitance and conductance.FindingsResults presented show that the threshold voltage is decreasing with stress time, the capacitance and conductance curves are altered by applied stress, also the oxide traps and the interface traps densities are increasing with stress time.Originality/valueThe positive bias stress seems to be more destructive in the case of the studied devices.

A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

n -channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (VDMOSFET) devices were subjected to a high electric field stress or to a x-ray radiation. The current-voltage and capacitance-voltage measurements show that the channel-side interface and the drain-side interface are affected differently in the case of high electric field stress, whereas the interfaces are nearly uniformly affected in the case of x-ray radiation. This paper also shows that for the gated diode structure of VDMOSFET, the direct-current current-voltage technique measures only the drain-side interface; the subthreshold current-voltage technique measures only the channel-side interface; and the capacitance-voltage technique measures both interfaces simultaneously and clearly distinguishes the two interfaces. The capacitance-voltage technique is suggested to be a good quantitative method to examine both interface regions by a single measurement.

Comparison between post-irradiation annealing and post-high electric field stress annealing of n-channel power VDMOSFETs

The behavior of the defects created in the gate oxide and at the Si/SiO 2 interface of n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) by irradiation and positive high electric field stress have been investigated. Interface traps exhibit the same behavior after both types of stress, while there are significant differences in post-stress responses of the charge trapped in the oxide, consisting of fixed and switching component.

VDMOSFET model parameter extraction based on electrical and optical measurements

Lateral device parameters for VDMOSFET (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) with hexagonal cells are extracted using an original method based on electrical and optical measurements. Using microscopic observation of the ship of the device and C–V characterization, the lateral device structure parameters could be extracted. Values of the extracted parameters are in good agreement with the values given by the manufacturer. The advantage of this method is the high precision of results for a low cost. Perhaps the most important point of this method is that it can replace the other techniques usually employed, wherein devices are destroyed to obtain the cross section of the structure. The proposed technique can be very useful for analyzing any complex geometrical structure of VDMOS transistors (hexagonal, triangular, square etc…).

VDMOSFET Model Parameter Extraction Based on Electrical and Optical Measurements

Lateral Device parameters for VDMOSFET (Vertical double diffused metal oxide semiconductor field effect transistor) with hexagonal cells has been extracted by an original model based on electrical and optical measurements. Using microscopic observation for the ship of the device and by C-V characterization, the lateral device structure parameters could be extracted. Values of the extracted parameters are in good correlation with the values given by the manufactured. Advantage of this model the high precision results with a low cost. Perhaps, the most important point in this model, that we can replace the other techniques usually employed in this study where we destroyed the device for cut and cross section of the structure. The proposed technique in this paper can be very useful for analyzing any complex geometrical structure of VDMOS transistors (hexagonal, triangular, square <em>etc</em>...).

Molybdenum Film Technology For Power Metal Oxide Semiconductor Field Effect Transistor Gate Electrode Applications

Molybdenum (Mo) film as a gate electrode for high-frequency power metal oxide semiconductor field effect transistor (MOSFET) has been investigated. The Mo films were deposited by sputtering in Ar ambient. The Mo films properties depend greatly on the substrate temperature. An accurate pattern was realized for Mo film. Stability and reliability of Mo gates for high-frequency power vertical double-diffused metal oxide semiconductor field effect transistors (VDMOSFETs) are as good as those of polysilicon gates. The shift of threshold voltage is below ±35 mV and the change of gate-source leakage current is less than 5 nA under the stress condition of ±5 MV/cm for 100 h at 250°C. Power gain and drain efficiency improvement of Mo gates for VDMOSFETs have been obtained.