VeloPix ASIC Research Articles

The LHCb vertex locator upgrade — the detector calibration overview

The Vertex Locator (VELO) is a silicon tracking detector in the spectrometer of the Large Hadron Collider beauty (LHCb) experiment. LHCb explores and investigates CP violation phenomena in b- and c- hadron decays and is one of the experiments operating on the Large Hadron Collider (LHC) at CERN. After run 1 and run 2 of LHC data taking (2011–2018), the LHCb detectors are being modernized within the LHCb upgrade I program. The upgrade aims to adjust the spectrometer to readout at full LHC 40 MHz frequency, which requires radical changes to the technologies currently used in LHCb. The hardware trigger is removed, and some of the detectors replaced. The VELO changes its tracking technology and silicon strips are replaced by 55 μm pitch silicon pixels. The readout chip for the VELO upgrade is the VeloPix ASIC. The number of readout channels increases to over 40 million, and the hottest ASIC is expected to produce the output data rate of 15 Gbit/s. New conditions challenge the software and the hardware side of the readout system and put special attention on the detector monitoring. This paper presents the upgraded VELO design and outlines the software aspects of the detector calibration in the upgrade I. An overview of the challenges foreseen for the upgrade II is given.

The upgrade I of LHCb VELO—towards an intelligent monitoring platform

The Large Hadron Collider beauty (LHCb) detector is designed to detect decays of b- and c- hadrons for the study of CP violation and rare decays. At the end of the LHC Run 2, many of the LHCb measurements remained statistically dominated. In order to increase the trigger yield for purely hadronic channels, the hardware trigger will be removed, and the detector will be read out at 40 MHz. This, in combination with the five-fold increase in luminosity, requires radical changes to LHCb's electronics, and, in some cases, the replacement of entire sub-detectors with state-of-the-art detector technologies. The Vertex Locator (VELO) surrounding the interaction region is used to reconstruct the collision points (primary vertices) and decay vertices of long-lived particles (secondary vertices). The upgraded VELO will be composed of 52 modules placed along the beam axis divided into two retractable halves. The modules will each be equipped with 4 silicon hybrid pixel tiles, each read out by 3 VeloPix ASICs. The total output data rate anticipated for the whole detector will be around 1.6 Tbit/s. The highest occupancy ASICs will have pixel hit rates of approximately 900 Mhit/s, with the corresponding output data rate of 15 Gbit/s. The LHCb upgrade detector will be the first detector to read out at the full LHC rate of 40 MHz. The VELO upgrade will utilize the latest detector technologies to read out at this rate while maintaining the required radiation-hard profile and minimizing the detector material.

Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of ~40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at ~5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above ~900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.

The LHCb Vertex Locator Upgrade

The Large Hadron Collider beauty LHCb detector is a dedicated flavour physics experiment, designed to efficiently detect decays of b- and c-hadrons to perform precise studies of CP violation and rare decays. At the end of Run 2, many of the LHCb measurements will remain statistically dominated. In order to increase the trigger yield for purely hadronic channels, the hardware trigger will be removed, and the full detector will be read out at 40 MHz. This, in combination with the five-fold increase in luminosity necessitates radical changes to LHCb's electronics with entire subdetector replacements required in some cases. The Vertex Locator (VELO) surrounding the interaction region is used to reconstruct the proton-proton collision points (primary vertices) and decay vertices of long-lived particles (secondary vertices). The upgraded VELO will be equipped with silicon hybrid pixel sensors, each read out by VeloPix ASICs. The highest occupancy ASICs will have pixel hit rates of 900 Mhit/s and produce an output data rate of over 15 Gbit/s, with a total rate of 1.6 Tbit/s anticipated for the whole detector. Selected highlights of this challenging and ambitious project are described in this paper.

On-detector Electronics for the LHCb VELO Upgrade

The LHCb Experiment is designed for precision measurements of CP violation and rare decays of beauty and charm hadrons. The experiment will be upgraded to a trigger-less system reading out the full detector at a 40 MHz event rate with all selection algorithms executed in a CPU farm. The upgraded Vertex Locator will be a hybrid pixel detector read out by the VeloPix ASIC with on-chip zero-suppression. The overview of the system and the design of the VELO on-detector electronics that include the front-end hybrid, the opto-conversion and power distribution boards will be summarised. The results from the evaluation of these prototypes and further enhancement techniques will be discussed.

SPIDR, a general-purpose readout system for pixel ASICs

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a “soft core” CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

The LHCb Vertex Locator (VELO) Pixel Detector Upgrade

The LHCb experiment is designed to perform high-precision measurements of CP violation and the decays of beauty and charm hadrons at the Large Hadron Collider (LHC) at CERN. There is a planned upgrade during Long Shutdown 2 (LS2), expected in 2019, which will allow the detector to run at higher luminosities by transforming the entire readout to a trigger-less system. This will include a substantial upgrade of the Vertex Locator (VELO), the silicon tracker that surrounds the LHCb interaction region. The VELO is moving from silicon strip technology to hybrid pixel sensors, where silicon sensors are bonded to VeloPix ASICs. Sensor prototypes have undergone rigorous testing using the Timepix3 Telescope at the SPS, CERN. The main components of the upgrade are summarised and testbeam results presented.

The VeloPix ASIC

VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in trigger-less mode, with event selection being performed in the CPU farm. The highest occupancy ASICs will experience rates of more than 900 Mhits/s, and the closest pixels are 5.1 mm from the LHC beams. This paper will present the VeloPix ASIC along with the first test results without a sensor.

LHCb VELO upgrade

The upgrade of the LHCb experiment, scheduled for LHC Run-III, scheduled to start in 2021, will transform the experiment to a trigger-less system reading out the full detector at 40MHz event rate. All data reduction algorithms will be executed in a high-level software farm enabling the detector to run at luminosities of 2×1033cm−2s−1.The Vertex Locator (VELO) is the silicon vertex detector surrounding the interaction region. The current detector will be replaced with a hybrid pixel system equipped with electronics capable of reading out at 40MHz. The upgraded VELO will provide fast pattern recognition and track reconstruction to the software trigger. The silicon pixel sensors have 55×55μm2 pitch, and are read out by the VeloPix ASIC, from the Timepix/Medipix family. The hottest region will have pixel hit rates of 900Mhits/s yielding a total data rate of more than 3Tbit/s for the upgraded VELO. The detector modules are located in a separate vacuum, separated from the beam vacuum by a thin custom made foil. The foil will be manufactured through milling and possibly thinned further by chemical etching.The material budget will be minimised by the use of evaporative CO2 coolant circulating in microchannels within 400μm thick silicon substrates. The current status of the VELO upgrade is described and latest results from operation of irradiated sensor assemblies are presented.

The LHCb VELO Upgrade

The LHCb detector has operated successfully during the first LHC run and produced many world-leading measurements. The collaboration is now preparing for an upgrade that will be installed in 2018-2019 to fully exploit the flavour potential of the LHC. The whole detector will be read out at the full bunch-crossing frequency implementing the online event selection in software. This will require major upgrades of all detector systems. The VELO will be replaced with a hybrid pixel detector with planar silicon sensors read out by the VeloPix ASIC, transmitting the data on high speed serial links to the off detector electronics. The detector modules will be cooled by an evaporative CO2 system with the coolant circulating in etched microchannels in the silicon cooling plate of the module. The performance of the upgraded detector has been studied with simulations and is shown to match or exceed that of the current VELO.

Developments towards the LHCb VELO upgrade

The Vertex Locator (VELO) is a silicon strip detector surrounding the interaction region of the LHCb experiment. The upgrade of the VELO is planned to be installed in 2019–2020, and the current detector will be replaced by a hybrid pixel system equipped with electronics capable of reading out at a rate of 40MHz. The new detector is designed to withstand the radiation dose expected at an integrated luminosity of 50fb−1. The detector will be composed of silicon pixel sensors, read out by the VeloPix ASIC that is being developed based on the TimePix/MediPix family. The prototype sensors for the VELO upgrade are being irradiated in five different facilities and the post-irradiation performance is being measured with testbeams, and in the lab. These proceedings present the VELO upgrade and briefly discuss the results of the sensor testing campaign.

The LHCb VELO upgrade

The upgrade of the LHCb experiment, planned for 2019, will transform the experiment to a trigger-less system reading out the full detector at 40MHz event rate. All data reduction algorithms will be executed in a high-level software farm. The upgraded detector will run at luminosities of 2×1033cm−2s−1 and probe physics beyond the Standard Model in the heavy flavour sector with unprecedented precision. The Vertex Locator (VELO) is the silicon vertex detector surrounding the interaction region. The current detector will be replaced with a hybrid pixel system equipped with electronics capable of reading out at 40MHz. The detector comprises silicon pixel sensors with 55×55μm2 pitch, read out by the VeloPix ASIC, based on the TimePix/MediPix family. The hottest region will have pixel hit rates of 900Mhits/s yielding a total data rate more than 3Tbit/s for the upgraded VELO. The detector modules are located in a separate vacuum, separated from the beam vacuum by a thin custom made foil. The detector halves are retracted when the beams are injected and closed at stable beams, positioning the first sensitive pixel at 5.1mm from the beams. The material budget will be minimised by the use of evaporative CO2 coolant circulating in microchannels within 400μm thick silicon substrates.

Upgrade of the LHCb Vertex Locator

The upgrade of the LHCb experiment, planned for 2018, will transform the entire readout to a trigger-less system operating at 40 MHz. All data reduction algorithms will be executed in a high-level software farm, with access to all event information. This will enable the detector to run at luminosities of 1–2 × 1033/cm2/s and probe physics beyond the Standard Model in the heavy sector with unprecedented precision.The upgraded VELO must be low mass, radiation hard and vacuum compatible. It must be capable of fast pattern recognition and track reconstruction and will be required to drive data to the outside world at speeds of up to 2.5 Tbit/s. This challenge is being met with a new Vertex Locator (VELO) design based on hybrid pixel detectors positioned to within 5 mm of the LHC colliding beams. The sensors have 55 × 55 μm square pixels and the VELOPix ASIC which is being developed for the readout is based on the Timepix/Medipix family of chips. The hottest ASIC will have to cope with pixel hit rates of up to 900 MHz.The material budget will be optimised with the use of evaporative CO2 coolant circulating in microchannels within a thin silicon substrate. Microchannel cooling brings many advantages: very efficient heat transfer with almost no temperature gradients across the module, no CTE mismatch with silicon components, and low material contribution. This is a breakthrough technology being developed for LHCb.LHCb is also focussing effort on the construction of a lightweight foil to separate the primary and secondary LHC vacua, the development of high speed cables and radiation qualification of the module.The 40 MHz readout will also bring significant conceptual changes to the way in which the upgrade trigger is operated. Work is in progress to incorporate momentum and impact parameter information into the trigger at the earliest possible stage, using the fast pattern recognition capabilities of the upgraded detector.The current status of the VELO upgrade will be described together with a presentation of recent beam-test results.

VeloPix ASIC development for LHCb VELO upgrade

The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500MHz, highly non-uniformly distributed over the 2cm2 chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip.