Vector Pipeline Research Articles

A novel optimization approach to topology checking of pipeline vector data in browser side

A novel optimization approach to topology checking of pipeline vector data in browser side

A Hypertuned Pipeline Vector Using Meta Classifier Technique for Feature Selection in Multi Disease Prediction

Automation of health sector plays a very important role especially during this pandemic due to the side effects of either vaccination or attack of the COVID. Most of the researchers designed a system to predict whether a person suffers from a particular disease or not. Few researchers worked on prediction variants of a single disease based on symptoms but due to this COVID-19, different people are getting attacked with different diseases as a side effect. This proposed system aims to identify the multiple diseases that a person may suffer from based on the symptoms. In this paper, the dataset obtained from the open access repository “Kaggle” contains 17 symptoms combinations to identify the one of the 41 types of diseases as class label. All the symptoms may not be important for identification, so in this model, the important features are identified using the pipeline vector of different Machine Learning approaches are passed as base line classifier and decision tree classifier as meta line to the elimination function. The model has got “99.48%” accuracy for selecting the essential features using bagging and boosting algorithms.

Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications

This paper describes the work carried out to extend the NOEL-V platform to include data-level parallelism (DLP) by implementing an integer subset of the RISC-V Vector Extension. The performance and resource utilization efficiency of the resulting vector processor for different levels of DLP (i.e., number of lanes) have been compared to the baseline scalar processor on a Xilinx Kintex Ultrascale field-programmable gate array, employing typical kernels for compute-intensive applications. The role of the memory subsystem has also been investigated, comparing the results obtained with a low-latency and a high-latency main memory. The results show that the speed-up due to the use of the vector pipeline increases with the number of lanes in the vector processor, achieving up to 23.0× the performance of the scalar processor with only 4.3× the resources of the baseline scalar processor. Using an implementation with 32 lanes increases performance even for problem sizes larger than the number of lanes, achieving up to more than 11.7× the performance of the scalar processor with just 1.9× its resource utilization for matrix multiplications. This work proves that implementations of the selected subset are easily scalable and fit for small-processor implementations in highly constrained space embedded systems.

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs

The use of artificial intelligence (AI) in sensor analytics is entering a new era based on the use of ubiquitous embedded connected devices. This transformation requires the adoption of design techniques that reconcile accurate results with sustainable system architectures. As such, improving the efficiency of AI hardware engines as well as backward compatibility must be considered. In this paper, we present the Hybrid-Float6 (HF6) quantization and its dedicated hardware design. We propose an optimized multiply-accumulate (MAC) hardware by reducing the mantissa multiplication to a multiplexor-adder operation. We exploit the intrinsic error tolerance of neural networks to further reduce the hardware design with approximation. To preserve model accuracy, we present a quantization-aware training (QAT) method, which in some cases improves accuracy. We demonstrate this concept in 2D convolution layers. We present a lightweight tensor processor (TP) implementing a pipelined vector dot-product. For compatibility and portability, the 6-bit floating-point (FP) is wrapped in the standard FP format, which is automatically extracted by the proposed hardware. The hardware/software architecture is compatible with TensorFlow (TF) Lite. We evaluate the applicability of our approach with a CNN-regression model for anomaly localization in a structural health monitoring (SHM) application based on acoustic emission (AE). The embedded hardware/software framework is demonstrated on XC7Z007S as the smallest Zynq-7000 SoC. The proposed implementation achieves a peak power efficiency and run-time acceleration of 5.7 GFLOPS/s/W and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$48.3\times $ </tex-math></inline-formula> , respectively.

Performance of GeantV EM Physics Models

The recent progress in parallel hardware architectures with deeper vector pipelines or many-cores technologies brings opportunities for HEP experiments to take advantage of SIMD and SIMT computing models. Launched in 2013, the GeantV project studies performance gains in propagating multiple particles in parallel, improving instruction throughput and data locality in HEP event simulation on modern parallel hardware architecture. Due to the complexity of geometry description and physics algorithms of a typical HEP application, performance analysis is indispensable in identifying factors limiting parallel execution. In this report, we will present design considerations and preliminary computing performance of GeantV physics models on coprocessors (Intel Xeon Phi and NVidia GPUs) as well as on mainstream CPUs.

An Energy Scaled and Expanded Vector-Based Forwarding Scheme for Industrial Underwater Acoustic Sensor Networks with Sink Mobility.

Industrial Underwater Acoustic Sensor Networks (IUASNs) come with intrinsic challenges like long propagation delay, small bandwidth, large energy consumption, three-dimensional deployment, and high deployment and battery replacement cost. Any routing strategy proposed for IUASN must take into account these constraints. The vector based forwarding schemes in literature forward data packets to sink using holding time and location information of the sender, forwarder, and sink nodes. Holding time suppresses data broadcasts; however, it fails to keep energy and delay fairness in the network. To achieve this, we propose an Energy Scaled and Expanded Vector-Based Forwarding (ESEVBF) scheme. ESEVBF uses the residual energy of the node to scale and vector pipeline distance ratio to expand the holding time. Resulting scaled and expanded holding time of all forwarding nodes has a significant difference to avoid multiple forwarding, which reduces energy consumption and energy balancing in the network. If a node has a minimum holding time among its neighbors, it shrinks the holding time and quickly forwards the data packets upstream. The performance of ESEVBF is analyzed through in network scenario with and without node mobility to ensure its effectiveness. Simulation results show that ESEVBF has low energy consumption, reduces forwarded data copies, and less end-to-end delay.

An emerging adeno-associated viral vector pipeline for cardiac gene therapy.

The naturally occurring adeno-associated virus (AAV) isolates display diverse tissue tropisms in different hosts. Robust cardiac transduction in particular has been reported for certain AAV strains. Successful applications of these AAV strains in preclinical and clinical settings with a focus on treating cardiovascular disease continue to be reported. At the same time, these studies have highlighted challenges such as cross-species variability in AAV tropism, transduction efficiency, and immunity. Continued progress in our understanding of AAV capsid structure and biology has provided the rationale for designing improved vectors that can possibly address these concerns. The current report provides an overview of cardiotropic AAV, existing gaps in our knowledge, and newly engineered AAV strains that are viable candidates for the cardiac gene therapy clinic.

An Emerging Adeno-Associated Viral Vector Pipeline for Cardiac Gene Therapy

An Emerging Adeno-Associated Viral Vector Pipeline for Cardiac Gene Therapy

A C-Based Variable Length and Vector Pipeline Architecture Design Methodology and Its Application

The size and performance of a System LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the System LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based variable length and vector pipeline (VVP) architecture design methodology and apply it to the design of the output probability computation circuit for a speech recognition system. VVP processing accelerated by loop optimization, memory access methods, and application-specific cir- cuit design was implemented to calculate the Hidden Markov Model (HMM) output probability at high speed and its performance is evaluated. It is shown that designers can explore a wide range of design choices and generate complex circuits in a short time by using a C-based pipeline architecture design method.

A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications

A very low-power MPEG-4 video decoder LSI for mobile applications is presented. A 27-MHz 16-b DSP with a vector pipeline architecture, four 27-MHz dedicated hardware engines for accelerating MPEG-4 visual SP@L1 decoding and post video processing, 896 Kb of embedded SRAM for storing reference images and bitstreams, and three peripheral blocks are integrated together on a single chip. The architecture of the DSP is optimized in terms of power consumption and performance. MPEG-4 visual SP@L1 decoding and post-video processing at low operating frequencies are realized using a hybrid architecture consisting of the DSP and the dedicated hardware engines. Clock gating is used extensively to reduce the power consumption of the processor. The processor has high reusability because it does not use process-dependent technology such as V/sub DD/-hopping and variable threshold voltages. The chip is implemented using 0.18-/spl mu/m CMOS technology. Its die area is 37 mm/sup 2/ and the power consumption is 11 mW at 1.5 V.

Pipeline vectorization

This paper presents pipeline vectorization, a method for synthesizing hardware pipelines based on software vectorizing compilers. The method improves efficiency and ease of development of hardware designs, particularly for users with little electronics design experience. We propose several loop transformations to customize pipelines to meet hardware resource constraints while maximizing available parallelism. For runtime reconfigurable systems, we apply hardware specialization to increase circuit utilization. Our approach is especially effective for highly repetitive computations in digital signal processor (DSP) and multimedia applications. Case studies using field programmable gate arrays (FPGAs)-based platforms are presented to demonstrate the benefits of our approach and to evaluate tradeoffs between alternative implementations. For instance, the loop-tiling transformation, has been found to improve vectorization performance 30-40 times above a PC-based software implementation, depending on whether runtime reconfiguration (RTR) is used.

Analysis and simulation of an out-of-order execution model in vector multiprocessor systems

Memory conflict is a major phenomenon which may cause dramatic loss of performance in vector pipeline multiprocessors. Various techniques have been proposed and implemented to avoid such conflicts. They rely mostly on well-tuned vector element allocation in memory banks (either using programming tools or hard-wired features). We tackle this problem in another way. Instead of trying to avoid memory contention, we aim to enhance the performance of the memory system by scheduling vector element accesses in order to increase memory accesses. This scheduling depends on the memory bank activity when an access is issued, leading to out-of-order access to vector elements. An out-of-order pipeline execution is associated with this out-of-order memory access in order to maintain the processor functional unit chaining. In this paper we study some factors influencing this execution model: vector length, number of processors and number of banks. An analysis of this model using the Markov chain technique and simulation results are also presented. They show the importance of this model in comparison with the classical one encountered in pipelined vector supercomputers.

Improvement of efficiency in generating random U(1) variables with Boltzmann distribution (von mises distribution revisited)

A method for generating random U(1) variables with Boltzmann distribution (i.e., realizing von Mises distribution) is presented. Based on the rejection method, high efficiency is achieved for the whole range of temperatures or coupling parameters, which makes the present method especially suitable for (parallel or pipeline) vector processing machines. Results of computer runs are presented to illustrate the efficiency. An idea to find the algorithm is presented, which is applicable to other distributions of interest in Monte Carlo simulations.

K-Dimensional Optimal Parallel Algorithm for the solution of a general class of recurrence equations

This paper proposes a parallel algorithm, called KDOP (K-Dimensional Optimal Parallel algorithm), to solve a general class of recurrence equations efficiently. The KDOP algorithm partitions the computation into a series of subcomputations, each of which is executed in the fashion that all the processors work simultaneously with each one executing an optimal sequential algorithm to solve a subcomputation task. The algorithm solves the equations inO(N/p) steps in EREW PRAM model (Exculsive Read Exclusive Write Parallel Random Access Machine model) usingp≤N1-∈ processors, whereN is the size of the problem, and ∈ is a given constant. This is an optimal algorithm (its speedup isO(p)) in the case ofp≤N1-∈. Such an optimal speedup for this problem was previously achieved only in the case ofp≤N0.5. The algorithm can be implemented on machines with multiple processing elements or pipelined vector machines with parallel memory systems.

Exploiting Data Structure Locality in the Dataflow Model

Although the dataflow model has been shown to allow the exploitation of parallelism at all levels, research of the past decade has revealed several fundamental problems. Synchronization at the instruction level, token matching, coloring, and re-labeling operations have a negative impact on performance by significantly increasing the number of non-compute "overhead" cycles. Recently, many novel hybrid von-Neumann data driven machines have been proposed to alleviate some of these problems. The major objective has been to reduce or eliminate unnecessary synchronization costs through simplified operand matching schemes and increased task granularity. Moreover, the results from recent studies quantifying locality suggest sufficient spatial and temporal locality is present in dataflow execution to merit its exploitation. In this paper we present a data structure for exploiting locality in a data driven environment: the vector cell. A vector cell consists of a number of fixed length chunks of data elements. Each chunk is tagged with a presence bit, providing intra-chunk strictness and inter-chunk non-strictness to data structure access. We describe the semantics of the model, processor architecture and instruction set as well as a Sisal to dataflow vectorizing compiler back-end. The vector cell model is evaluated by comparing its performance to those of both a classical fine-grain dataflow processor employing I-structures and a conventional pipelined vector processor. Results indicate that the model is surprisingly resilient to long memory and communication latencies and is able to dynamically exploit the underlying parallelism across multiple processing elements at run time.

Air streams in the atmosphere induced by multiple near-surface heat sources

On the basis of the complete system of unsteady Navier-Stokes equations for a compressible heat-conducting gas the authors have developed a numerical method for solving the three-dimensional problem of the theory of convection designed for an EC 1037-EC 2706 vector pipeline system. The problem of the ascent and interaction in the atmosphere of seven large-scale thermals generated close to the ground is solved.

A method of vector processing for shared symbolic data

Conventional processing techniques for pipelined vector processors such as the CRAY-XMP, or data-parallel computers, such as the Connection Machines, are generally applied only to independent multiple data processing. This paper describes a vector processing method for multiple processings including parallel rewriting of dynamic data structures with shared elements, and for multiple processings that may rewrite the same data item multiple times. This method enables vector processing when entering multiple data items into a hash table, address calculation sorting, and many other algorithms that handle lists, trees, graphs and other types of symbolic data structures. This method is applied to several algorithms; consequently, the performance is improved by a factor of ten on a Hitachi S-810.

Gravity field determination using boundary element methods

The Boundary Element Method (BEM), a numerical technique for solving boundary integral equations, is introduced to determine the earth's gravity field. After a short survey on its main principles, we apply this method to the fixed gravimetric boundary value problem (BVP), i.e. the determination of the earth's gravitational potential from measurements of the intensity of the gravity field in points on the earth's surface. We show how to linearize this nonlinear BVP using an implicit function theorem and how to transform the linearized BVP into a boundary integral equation using the single layer representation. A Galerkin method is used to transform the boundary integral equation using the single layer representation. A Galerkin method is used to transform the boundary integral equation into a linear system of equations. We discuss the major problems of this approach for setting up and solving the linear system. The BVP is numerically solved for a bounded part of the earth's surface using a high resolution reference gravity model, measured gravity values of high density, and a 50 ⋅ 50 m2 digital terrain model to describe the earth's surface. We obtain a gravity field resolution of 1 ⋅ 1 km2 with an accuracy of the order 10−3 to 10−4 in about 1 CPU-hour on a Siemens/Fujitsu SIMD vector pipeline machine using highly sophisticated numerical integration techniques and fast equation solvers. We conclude that BEM is a powerful numerical tool for solving boundary value problems and may be an alternative to classical geodetic techniques.

Real-time vector pipeline colour space transformer

The design and implementation, using custom ICs, of a new real-time vector pipeline colour space transformer, which performs the transformation of the RGB colour coordinates to chromaticity coordinates is presented. Its minimum rate of operation is 66-5 MIPS and it can handle high resolution colour images of up to 682pizels per horizontal line. The high speed of operation was achieved by pipelining the data in a vector fashion. The device is intended to be used as the front end of colour machine vision systems in industrial pattern recognition, where the need for short processing times is crucial.