The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.