This paper contains the design consideration of 18nm FDSOI MOSFET for mitigating the self-heating effects. As the device scaling reaches towards the nano regime, self-heating effects are quite significant. Increase in the lattice temperature will lead to decrease in the mobility and degradation of the drain current. Self-heating effects are investigated in FDSOI MOSFET by comparing different physical parameter variations like gate length, spacer thickness, buried oxide thickness and source/drain/metal contacts. It is being observed that the heat sinks used as metal contacts can reduce lattice temperature up to 62% and spacer size thickness can reduce it by 10%. However the buried oxide box thickness and gate length modifications do not have considerable impact on the self-heating.
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