Unsigned Multiplier Research Articles

Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification

One promising approach to verify large arithmetic circuits is making use of Symbolic Computer Algebra (SCA), where the circuit and the specification are translated to a set of polynomials, and the verification is performed by the ideal membership testing. Here, the main problem is the monomial explosion for buggy arithmetic circuits, which makes obtaining the word-level remainder become unfeasible. So, automatic correction of such circuits remains a significant challenge. Our proposed correction method partitions the circuit based on primary output bits and modifies the related Groebner basis based on the given suspicious gates, which makes it independent of the word-level remainder. We have applied our method to various signed and unsigned multipliers, with various sizes and numbers of suspicious and buggy gates. The results show that the proposed method corrects the bugs without area overhead. Moreover, it is able to correct the buggy circuit on average 51.9× and 45.72× faster in comparison with the state-of-the-art correction techniques, having single and multiple bugs, respectively.

Two energy efficient unsigned approximate multipliers with N-4 compressors

Two energy efficient unsigned approximate multipliers with N-4 compressors

Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

Enhancing ASIC chip performance through integrated algorithm optimization

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

A regular architecture for a low-quantum-cost n-bit multiplier

Multiplication is a fundamental operation in quantum circuits that plays a crucial role in many quantum algorithms and applications. This manuscript proposes a new architecture for an n-bit unsigned multiplier based on a regular structure consisting of Feynman gates for duplication, BME gates for partial multiplication, and HNG and Peres gates for the final adder part. The proposed multiplication technique is compared with previous research circuits, and the results demonstrate that it has a better quantum cost. The proposed architecture has the potential to significantly improve the efficiency and performance of quantum multipliers. On average, the proposed design gains an improvement of 15.7 % in terms of quantum cost over the best-known existing approach. The proposed architecture has several advantages over existing approaches, such as regularity, simplicity, and lower quantum cost.

FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder

In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding method. While this more advanced technology includes many approximate multipliers, it sacrifices the ability to find the closest integer of a rounded value when combining signed and unsigned capabilities, resulting in higher absolute errors than other approximate multipliers based on rounding. This proposed work will introduce a novel method of Truncated Shifter Rounding-based Approximate Multiplier integrated with a High-Level Synchronous XOR-MUX Full Adder design to minimize the number of logic gates and power consumption in the multiplier architecture. The Truncated RoBA (Rounding-based Approximate Multiplier) with XOR MUX Full Adder will reduce the logic size in the shifter and the arithmetic circuit. The work will modify this rounding-based approximate multiplier to minimize area, delay, and power consumption. This proposed architecture will be integrated with two fundamental changes: firstly, its Barrel shifter method will be replaced with a truncated shifter multiplier with XOR MUX Full Adder, and secondly, the parallel prefix Brent Kung adder will be replaced with a carrying-save adder with XOR MUX Full Adder. Finally, this architecture was designed using Verilog-HDL and synthesized using the Xilinx Vertex-5 FPGA family, targeting the device Xc7Vx485tFFg1157-1. It resulted in a reduction of area LUT (34%), power (1%), delay (32%), and error analysis (75%) when compared to the existing RoBA.

Improved approximate multiplier architecture for image processing and neural network applications

This paper proposes new approximate unsigned multiplier architecture which aims to reduce the power consumption and area with better accuracy. In our proposed design, the approximation is applied in partial product generation (PPG) and partial product reduction (PPR) stages. In PPG, we proposed two approximate sub-multipliers to reduce the number of partial product rows. For the 8-bit multiplier design, experimental results show an improvement of 38.78% and 50.53% in power and power-delay-product respectively, when the proposed design is compared against the exact design, and 26.11% and 33.17% respectively when compared to existing Ax8-1 design, without compromising on the accuracy. Finally, proposed designs are validated using image processing and neural network applications.

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Design methodology for highly accurate approximate multipliers for error resilient applications

Approximate computing has become the paradigm shift for applications such as neural networks and image processing, where accurate computation is not needed and intends to improve area, power, and speed. New Multiplier architectures are proposed in this paper based on an algorithm which assigns the appropriate approximate compressor adaptively from existing set of compressors to improve the accuracy in the corresponding partial product column. Experimental results prove that the existing unsigned multiplier architectures have less accuracy than the proposed designs. To quantify the performance of the proposed designs they were assessed using image processing and neural network applications. From the results, it can be deduced that the proposed architectures achieve up to 43% increase in PSNR when compared to the existing designs, with up to 14.3% increase in power consumption.

An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL

An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors

Approximate computing is a promising approach for reducing power consumption and design complexity in applications that accuracy is not a crucial factor. Approximate multipliers are commonly used in error-tolerant applications. This paper presents three approximate 4:2 compressors and two approximate multiplier designs, aiming at reducing the area and power consumption, while maintaining acceptable accuracy. The paper seeks to develop approximate compressors that align positive and negative approximations for input patterns that have the same probability. Additionally, the proposed compressors are utilized to construct approximate multipliers for different columns of partial products based on the input probabilities of the two compressors in adjacent columns. The proposed approximate multipliers are synthesized using the 28nm technology. Compared to the exact multiplier, the first proposed multiplier improves power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> delay and area <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> power by 91% and 86%, respectively, while the second proposed multiplier improves the two parameters by 90% and 84%, respectively. The performance of the proposed approximate methods was assessed and compared with the existing methods for image multiplication, sharpening, smoothing and edge detection. Also, the performance of the proposed multipliers in the hardware implementation of the neural network was investigated, and the simulation results indicate that the proposed multipliers have appropriate accuracy in these applications.

Design of an Approximate Multiplier with Time and Power Efficient Approximation Methods

Approximate multipliers have gradually become a focus of research due to the emergence of fault-tolerant applications. This paper deals with the approximation methods for an approximation multiplier with truncation, probability transformation and a majority gate-based compressor chain. With the help of probability analysis, the proposed approximation methods are utilized in an approximate [Formula: see text] unsigned multiplier to achieve low accuracy loss, high efficiency for time and power. Compared with the precise and approximate multipliers, the proposed design brings 55.0%, 39.0% reduction in delay and 73.8%, 22.6% power saving. The proposed multiplier achieves better peak signal-to-noise ratio (PSNR) values when evaluated with an image processing application.

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

Compressor based hybrid approximate multiplier architectures with efficient error correction logic

A new approximate unsigned multiplier architecture has been proposed in this paper, which aims to minimize the area utilized and power consumed while maintaining high accuracy. The proposed architecture is segmented into the least significant region (LSR), the approximate region, and the accurate region (most significant region). In LSR, the partial products (PPs) are reduced using four methods. In contrast, in the approximate region, two new approximate compressors are used to reduce the PPs, and the error arising from the approximate compressors is neutralized using an efficacious error-correcting module. For the 8-bit multipliers, the results indicate that the proposed designs, when compared against the exact design, achieve an increment of 26.5% and 32.2% in power and power-delay-product, respectively, and when compared with other approximate designs, achieve an improvement of 18.4% and 26.4%, respectively. Finally, proposed designs are evaluated using image processing and neural network applications.

Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements

Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> contiguous bits (a segment of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> bits) is extracted from each of the two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> -bits operand, the two segments are in input to a small <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times m$ </tex-math></inline-formula> internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications.

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module

This letter proposes an unsigned approximate multiplier architecture segmented into three portions: the least significant portion that contributes least to the partial product (PP) is replaced with a new constant compensation term to improve hardware savings without sacrificing accuracy. The PPs in the middle portion are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple yet efficient error correction module. The most significant portion of the multiplier is implemented using exact logic as approximating it will results in a large error. Experimental results of 8-bit multiplier show that the power and power-delay products are reduced up to 47.7% and 55.2%, respectively, in comparison with the exact design and 36.9% and 39.5%, respectively, in comparison with the existing designs without significant compromise on accuracy.

Performance analysis and implementation of approximate multipliers on spartan 6 FPGA

Multiplication is a frequently utilized mathematical operation in numerous applications, including signal processing, image processing, and multimedia applications, where multipliers are key components. The speed and large area typically limit their performance. Approximate computing has been critical. These programs are unable to take precise values in specific methods. In them, they like approximate values. Approximate computing methods are used to solve this problem. Approximate multipliers and compressors are constructed by utilizing approximate computation approaches. Because more complicated circuitry is used in many applications, such as DSP, these approximate multipliers and approximate compressors are useful. The suggested work is simulated with Verilog and synthesized with Xilinx ISE 14.6 before being implemented in Spartan – 6. The hardware, size, and speed performance of the suggested multipliers. Both signed and unsigned multipliers are subjected to the multipliers.

Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm

Multipliers are essential parts of every processor or computer. Microcontrollers and digital signal processors typically measure their performance on how many multiplications they can execute in a given amount of time. As a result, better multiplier designs are sure to increase system efficiency. A reversible Dadda multiplier is one such possible approach. The Dadda tree technique is used to construct two 32x32 reversible unsigned multipliers in this paper. The TG and FG gates are accustomed to create the partial product circuit in the first design. The PG and TG are utilized to create a partial product circuit in the second design. For adding partial products, the PG and reversible full adder gates are used. The design is implemented using Xilinx ISE 14.7 design suite.

On the design of radix-K approximate multiplier using 2D pseudo-booth encoding

In this paper, we propose energy-efficient unsigned approximate multipliers using the Pseudo-Booth (PB) encoding that are suitable for large dynamic-range operands thanks to leading zero remover (LZR) circuit. We have used our encoding form for both operands, so the proposed multiplier is called by two-dimensional Pseudo-Booth (2DPB) multiplier. The proposed multiplier accuracy can be adjusted by tuning the encoder radix and the truncation value. The efficiency of the proposed 2DPB multiplier has been evaluated by comparing its characteristics to those of six state-of-the-art approximate multipliers and the conventional (exact) multiplier in a TSMC-180 nm technology. The results reveal that the proposed 16-bit unsigned multiplier R8-T12, i.e., radix-8 and 12-bits truncation, provides up to 95% and 89% reductions in power-delay product (PDP) and power consumption, respectively, compared to the exact unsigned multiplier. It also provides up to 55% and 24.4% lower power-delay product (PDP), respectively, compared to the best of other approximate multipliers considered in this brief. Finally, the effectiveness of the proposed multiplier in real-life applications, including FIR filters and two image processing applications of smoothing and sharpening, is demonstrated.

Implementation of efficient MAC for DSP applications using Modified Booth Encoding algorithm technique

Multiplier and MAC is fundamental elements in DSP processors. Multiplication is one of the essential functions of arithmetic operation in computing systems, performing with different multipliers with different algorithms. MAC consisting of multiplier, adder and accumulator which plays a vital role in various DSP applications in improving signal processing ability, FIR and IIR filters. This article concentrates particularly on the efficient implementations of an accurate, signed and unsigned point multiplier. A modified booth Encoding (MBE) multiplier is used to execute a multiplier in floating point multiplier in order to significantly reduce partial products into half. CSA is applied with the inclusion of partial products in order into half. CSA is applied with the inclusion of partial products in order to improve speed.Rounding is not introduced to make the multiplier of a MAC unit more precise. Hence the proposed system shows an improved performance in systems area by 64.77%, reduced surplus power consumption by 44.41%, delay is reduced by 80% and shows a less circuit cost efficient. This proposed system area, power, delay, area delay product and power delay product are designed and calculated using synopsis, advanced VLSI tool.