Universal Circuit Research Articles

Design, Analysis and Optimization of a Universal Power Factor Correction Circuit for Linear Fluorescent Lamps

In this paper the analysis and optimization of a universal high power factor correction circuit for linear fluorescent lamps is presented. The design and analysis criteria for the converter include a universal voltage input, 120 to 277 V AC with power handling capability from no load to 110 watts. In addition a new PSPICE model for universal power factor correction circuit operating in the critical conduction mode has been developed. Simulation and analytical results have been validated against actual laboratory measurements.

Efficient implementation of cryptographically useful "large" boolean functions

We present low cost hardware architecture for implementing state-of-the-art theoretical constructions of secure Boolean functions suitable for stream ciphers. Using a pipelined architecture, we show that it is possible to implement systems which use Boolean functions of a relatively large number of variables. Our architecture is reconfigurable and provide a universal circuit for a certain class of secure Boolean functions.

A universal equivalent circuit model for the impedance response of composites

An equivalent circuit model has been developed to describe the impedance response of composites with insulating or conductive particles or fibers. Required inputs are the matrix conductivity, the “intrinsic conductivity” of the particles, and their volume fraction. The model has general applicability to systems involving moderately conductive matrices, insulating or conductive particles/fibers, and, in the case of conducting particles, the presence of a high impedance “coating” element on the particle surfaces. Ramifications for the use of impedance spectroscopy in the characterization of composite properties and the monitoring of their performance under load are discussed.

Robust and universal constant- g m circuit technique

A robust and universal circuit technique to maintain a constant transconductance, g/sub m/, in rail-to-rail amplifiers based on input stages made up of parallel-connected complementary differential pairs, is presented. The technique is universal, since it is valid regardless of the g/sub m//I/sub D/ characteristic of input devices. Also, the accuracy does not depend on any condition for matching n- to p-channel input transistors, which makes the technique robust. Experimental results obtained from a 0.8 /spl mu/m CMOS test-chip prototype, are given.

Power booster audio amplifier

A novel power booster amplifier is based on a modified half-bridge topology using separated switches and a floating bridge capacitor. The power booster amplifier provides four times higher peak power at the loudspeaker than the peak power of a class-D amplifier using the same power supply. Total harmonic distortion and amplifier efficiency are similar to a class-D amplifier. A universal integrated circuit supporting Class-D, boost bridge amplifiers and power booster amplifiers is proposed.

Self-repairable GALs

This paper describes the concept of self-testable and self-repairable Generic Array Logic (GAL) devices for high security and safety applications. A design methodology is proposed for self-repairing of a GAL which is a kind of Electrically Programmable Logic Devices (EPLDs). The fault-locating and fault-repairing architecture with electrically re-configurable GALs is presented. It uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair of all multiple stuck-at faults which might occur on E2CMOS cells in programmable AND plane. A self-repairing methodology is presented, based on our design architecture. A “column replacement” method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that a self-repairable GAL will last longer in the field. It gives also information on how many extra columns a GAL needs to reach a lifetime goal, in terms of simulation looping time, until the GAL is not useful any more. Therefore, an ideal point could be estimated, where the maximum reliability can be reached with the minimum cost.

Universal HSPICE macromodel for giant magnetoresistance memory bits

Nonvolatile semiconductor storage using giant magnetoresistance (GMR) memory bits has the potential for revolutionizing both high-density and high-speed memory applications with devices exhibiting unlimited write endurance and very low write energy. This paper presents the first universal circuit macromodel for GMR memory bits. The macromodel is realized as a four-terminal subcircuit that emulates GMR bit behavior over a wide range of sense and word-line currents. It realistically models the nonlinear and hysteretic behavior of GMR memory bits, their transient thermal behavior, and the sense-current dependency of their write thresholds. The model is flexible and relatively simple: Ranges of the write/read currents and bit resistance values are incorporated as parameterized variables, and no semiconductor devices are used within the model.

A Comparitive Study of A 1500 Calorie 40/30/30 Diet VS. 1500 Calorie Step 1 Diet on Body Composition and Blood Parameters in Overweight Adults

Twenty-nine overweight men and women (body mass >25) participated in this six week outpatient study. The participants were randomized to either a 1500 calorie 40/30/30 diet [40%CHO] (n=14) or a 1500 calorie Step 1 diet [60% CHO] (n=15). The 40/30/30 diet consisted of 40% CHO, 30% protein, 30% fat, the Step I Diet consisted of 60% CHO, 15% protein, and 25% fat. All subjects participated in Universal Circuit Training™, one hour, three times per week supervised by an exercise physiologist. All subjects met two to four times (avg.=3) over six weeks with a registered dietitian for review and analysis of compliance to the study diets. Both groups lost a significant amount of weight (p<0.05) after 6 weeks of treatment (40% CHO, -2.8 kg; 60% CHO, -1.2 kg). However, the 40% CHO group lost more weight and a greater amount of body fat (-2.6 kg; p<0.05), while the 60% CHO (-1.0 kg) group did not achieve significant fat loss. There were no significant changes for both groups in serum glucose, HgBA 1C, total cholesterol, high density lipoprotein, low density lipoprotein, or triglycerides during the study. Profile of Mood States (POMS) for fatigue and vigor was also analyzed in both study groups with the following results: 44% reduction in fatigue (p<0.05) for the 40% CHO group with a corresponding 15.7% increase in vigor (non-significant;p>0.05). The changes within the 60% CHO group did not achieve significance in either fatigue or vigor. In conclusion, the 1500 calorie 40/30/30 diet resulted in a significantly greater fat and weight loss compared with the 1500 calorie Step 1 diet over six weeks.

Chaos in ferroresonant wound voltage transformers: effect of core losses and universal circuit behaviour

The damping effects of transformer core losses upon the ferroresonant behaviour of wound instrument transformers, fed from a sinusoidal supply through circuit breaker grading capacitance, are studied using nonlinear dynamical methods. The system is shown to exhibit three types of ferroresonance; fundamental frequency ferroresonance, subharmonic ferroresonance and chaotic ferroresonance. It is also shown that this ferroresonant circuit can be driven into chaotic behaviour through a sequence of period-doubling bifurcations. Values of Feigenbaum universal number δ are calculated and are shown to be in good agreement with those reported from various other disciplines.

A universal circuit for studying chaotic phenomena

In this paper, an overview of the results on an autonomous chaotic electronic circuit, called Chua’s oscillator, is given. Along with brief descriptions of numerical and analytical investigations on Chua’s oscillator, we present some of its potential applications. The significance of the oscillator for the study of general dynamical systems is discussed.

Mini features

DDC has developed a universal interface circuit for commercial aircraft avionics which increases system reliability by a factor of nine and reduces pcb real estate by a factor of five. Each DD‐03232 circuit can accept 32 of the many hundreds of “discrete” signals used on commercial aircraft and interface them, via 8‐ or 16‐bit digital words, to the avionics systems.

Universal circuit matrix for adjacency graphs of feedback functions

We define the class of undirected graphs associated with the feedback functions. Next, we construct a mapping which transforms a given feedback function into the circuit matrix of the corresponding graph. This mapping establishes some linear dependences between the nonlinear feedback functions, so it may be a useful tool for the study of such functions.

A study on the development of an automatic fault diagnosis system for testing nuclear power plant digital electronic circuits

This paper describes a study on the development of an automatic fault diagnosis system for testing digital electronic circuits of nuclear power plants. Compared with the other conventional fault diagnosis systems, the system described in this paper uses Artificial Intelligence technique of model based reasoning and corroboration, which makes fault diagnosis much more efficient. Since the system diagnoses the circuit boards based only on input and output signals, it can be further developed for on-line testing. The system was implemented on a microprocessor and was applied for Universal Circuit board testing of the Solid State Protection System in nuclear power plants.

A universal circuit for studying and generating chaos. I. Routes to chaos

In this introductory tutorial paper, we demonstrate the generality of Chua's oscillator in generating chaos and bifurcation phenomena by electronic laboratory experiments which illustrate the standard routes to chaos, and by giving a result which shows that Chua's oscillator can generate the same qualitative behavior as any member of a 21-parameter family C of continuous, odd-symmetric, piecewise-linear vector field in R/sup 3/. This result is of fundamental importance because it unifies many previously published papers on chaotic circuits and systems under one umbrella, thereby obviating the need to analyze these circuits and systems as separate and unrelated systems. Indeed, every bifurcation and chaotic phenomena exhibited by any member of the family C is also exhibited by this universal circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A universal circuit for studying and generating chaos. II. Strange attractors

For pt. I see ibid., vol. 40, no. 10, p. 732-44 (1993). In a companion paper, we have shown how Chua's oscillator is topologically conjugate to a class of 3D systems. In this paper, we use this result to approximate other chaotic systems in the literature which are not necessarily piecewise linear. To further illustrate the complexity of Chua's oscillator, we also include a gallery of the many attractors found in Chua's oscillator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Generic oracles, uniform machines, and codes

The basic properties of generic oracles are reviewed, and proofs given that they separate P and NP and are weakly incompressible. A new notion of generic oracle, called t-generic, is defined. It is shown that t-generic oracles do not exist, and consequently a nondeterministic oracle machine which for any oracle X accepts the tautologies relativized to X when running with oracle X does not run in polynomial time at any oracle. A weak form of t-generic oracle, called r-generic, is shown to exist, and it is shown that if there exists an r-generic oracle X at which the r-query relativized tautologies are not in co NPX then NP ≠ co NP. The notion of a code for the Boolean functions is defined, and it is shown that generic oracles do not have short codes in any code. Universal circuits of size O(n log4 n) are shown to exist, and it is shown that increasing the number of ⋏, ⋎ gates from g to 2g + 1 allows the computation of new Boolean functions.

A Depth-Universal Circuit

This paper describes a family of depth-universal circuits. For any n, c, d there is a universal circuit $U(n,c,d)$ that can simulate any circuit $\alpha $ having n inputs, of size c and depth d, and U has depth $O(d)$ and size $O(c^3 d/\log c)$. The construction is used to give an alternative proof of a theorem of Ruzzo showing the invariance under different uniformity conditions of complexity classes defined by uniform circuit families.

Implementation of the unary operators in ternary logic : A universal CMOS circuit

A universal CMOS circuit for the implementation of the unary operators in ternary logic is presented. This circuit supplies simultaneously 12 of the 27 unary operators and, modifying its external connections, it is able to implement, all the unary operators. Further, this circuit includes only MOSFETs (So there is no resistance in its structure), its power dissipation is low and its switching times are standard. For the construction of this circuit, only easily obtainable chips are used.

No. 10A Remote Switching System: Remote Terminal Firmware

The No. 10A RSS remote terminal (RT) is a part of a distributed telephone switching system consisting of one or more remote terminals controlled by a host ESS via data link communication. The RT is a microprocessor-based peripheral controller acting as an extension of the host network. The RT firmware contains a process-oriented operating system. Ringing and other high-power signals are supplied by universal service circuits used in a time-sharing arrangement. The RT firmware is responsible for scanning lines and reporting supervisory state changes to the host. These changes are reported over either the data link or a channel, depending on the state of the line. If data link communication fails, the RT leaves the normal master/slave mode and enters a special stand-alone mode to provide a POTS-type intra-RT service.

Minimal realization of two-port parameters

A universal circuit realizing arbitrary two-port parameters given in the rational form is presented. The network uses the minimum number of grounded capacitors and only two multiple voltage controlled voltage sources. The approach presented is based on the transformation of the state matrices to the special forms which correspond to the network given in the ladder. The degree of freedom in selecting the ladder network element values can be used to minimize a certain performance function for sensitivity.