Ultrathin Equivalent Oxide Thickness Research Articles

Ultraflat single-crystal hexagonal boron nitride for wafer-scale integration of a 2D-compatible high-κ metal gate.

Hexagonal boron nitride (hBN) has emerged as a promising protection layer for dielectric integration in the next-generation large-scale integrated electronics. Although numerous efforts have been devoted to growing single-crystal hBN film, wafer-scale ultraflat hBN has still not been achieved. Here, we report the epitaxial growth of 4 in. ultraflat single-crystal hBN on Cu0.8Ni0.2(111)/sapphire wafers. The strong coupling between hBN and Cu0.8Ni0.2(111) suppresses the formation of wrinkles and ensures the seamless stitching of parallelly aligned hBN domains, resulting in an ultraflat single-crystal hBN film on a wafer scale. Using the ultraflat hBN as a protective layer, we integrate the wafer-scale ultrathin high-κ dielectrics onto two-dimensional (2D) materials with a damage-free interface. The obtained hBN/HfO2 composite dielectric exhibits an ultralow current leakage (2.36 × 10-6 A cm-2) and an ultrathin equivalent oxide thickness of 0.52 nm, which meets the targets of the International Roadmap for Devices and Systems. Our findings pave the way to the synthesis of ultraflat 2D materials and integration of future 2D electronics.

Impacts of Equivalent Oxide Thickness Scaling of TiN/Y₂O₃ Gate Stacks With Trimethylaluminum Treatment on SiGe MOS Interface Properties

Ultrathin equivalent oxide thickness (EOT) scaling of TiN/Y2O3 /SiGe gate stacks using a trimethylaluminum (TMA) treatment was studied. In comparison to previously reported high-k/SiGe MOS interfaces utilizing various Ge contents, we obtained an EOT scaling down to 1 nm with ultralow interface trap densities ( $\text{D}_{\text {it}}$ ). In addition, the impact of EOT scaling on the SiGe MOS interface properties has been investigated. We found the stress-induced degradation at the SiGe interface from constant gate biasing can be suppressed by scaling the thickness of Y2O3.

Reducing the power consumption of two-dimensional logic transistors

The growing demand for high-performance logic transistors has driven the exponential rise in chip integration, while the transistors have been rapidly scaling down to sub-10 nm. The increasing leakage current and subthreshold slope (SS) induced by short channel effect (SCE) result in extra heat dissipation during device operation. The performance of electronic devices based on two-dimensional (2D) semiconductors such as the transition metal dichalcogenides (TMDC) can significantly reduce power consumption, benefiting from atomically thin thickness. Here, we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors (MOSFETs) and 2D negative capacitance field effect transistors (NCFETs), outlining their potential in low-power applications as a technological option beyond scaled logic switches. Above all, we show our perspective at 2D low-power logic transistors, including the ultra-thin equivalent oxide thickness (EOT), reducing density of interface trap, reliability, operation speed etc. of 2D MOSFETs and NCFETs.

Electrical Properties of Ge pMOSFETs With Ultrathin EOT HfO2/AlO<italic>x</italic>/GeO<italic>x</italic>Gate-Stacks and NiGe Metal Source/Drain

The high performance Ge pMOSFETs have been realized with ultrathin HfO2/AlO x /GeO x /Ge gate-stacks fabricated by ozone postoxidation (OPO) and NiGe metal source/drain (S/D). It is found that OPO yields a reduction of interface traps and an improvement of dielectric strength for the HfO2/AlO x /GeO x /Ge gate-stacks. On the other hand, it is also confirmed that the NiGe metal S/D structure decreases the S/D parasitic resistance severely. As a result, the record high drive current has been realized under a comparable gate length for present Ge pMOSFET structure with the ultrathin equivalent oxide thickness HfO2/AlO x /GeO x /Ge gate-stack and the low parasitic resistance NiGe S/D.

Fabrication, Characterization, and Analysis of Ge/GeSn Heterojunction p-Type Tunnel Transistors

We present a detailed study on fabrication and characterization of Ge/GeSn heterojunction p-type tunnel-field-effect-transistors (TFETs). Critical process modules as high-k stack and p-i-n diodes are addressed individually. As a result an ultrathin equivalent oxide thickness of 0.84 nm with an accumulation capacitance of $3~\mu \text{F}$ /cm2 was achieved on an extremely scaled tri-layer stack of GeSnOx/Al2O3/HfO2 deposited by atomic-layer deposition monitored in situ by spectroscopic ellipsometry. Combining these process modules, Ge/GeSn heterojunction pTFETs are fabricated and characterized to demonstrate the best in-class pTFET performance in the GeSn material system. The transfer characteristics of the TFETs show signatures of the trap-assisted thermal generation in the subthreshold regime which is explained by a modified Shockley–Read–Hall model. For the ON-state current, we used band-to-band tunneling models calculated using parameters from the density functional theory. We then use the calibrated model to project performance of GeSn pTFETs with increased Sn content (lower bandgap), reduced trap density and ultrathin body geometry. Both experimental and projected results are benchmarked against state-of-the art III–V (e.g., In0.65Ga0.35/GaAs0.4Sb0.6) pTFETs. We demonstrate the ability of GeSn to achieve superior performance with both high ON-current and sub-60mV/decade switching benefiting from the small and direct bandgap for higher Sn contents.

Highly scaled equivalent oxide thickness of 0.66 nm for TiN/HfO2/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

Through in situ hydrogen plasma treatment (HPT) and plasma-enhanced atomic-layer-deposited TiN (PEALD-TiN) layer capping, we successfully fabricated TiN/HfO2/GaSb metal–oxide–semiconductor capacitors with an ultrathin equivalent oxide thickness of 0.66 nm and a low density of states of approximately 2 × 1012 cm−2 eV−1 near the valence band edge. After in situ HPT, a native oxide-free surface was obtained through efficient etching. Moreover, the use of the in situ PEALD-TiN layer precluded high-κ dielectric damage that would have been caused by conventional sputtering, thereby yielding a superior high-κ dielectric and low gate leakage current.

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al2O3/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al2O3/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1×1011cm−2eV−1 during a p-doping of 1×1018cm−3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO2 insulator.

Interface Characterization of HfO2/GaSb MOS Capacitors With Ultrathin Equivalent Oxide Thickness by Using Hydrogen Plasma Treatment

We investigate p-type GaSb MOS capacitors with various HfO2 thicknesses grown using an atomic layer deposition. GaSb surfaces treated with ex-situ chemical solution and in situ remote hydrogen plasma are inspected. After a series of etching steps, the GaSb surfaces exhibit smooth topography, indicating that this combination of treatments is capable of realizing ultrathin dielectric deposition. After etching processes, the ultrathin (approximately 3 nm) HfO2 layer deposited successfully on GaSb exhibit high-permittivity (approximately 21) properties as well as equivalent oxide thickness (EOT) of 0.75 nm, which can be attributed to the flat surface. To the best of our knowledge, the EOT of GaSb capacitor prepared using the exploited approach is record low. Furthermore, we find that the interlayer present after hydrogen plasma treatment and forming gas annealing could efficiently passivate interface state density and achieve high $C$ – $V$ modulation. Compared with the benchmark of gate leakage current versus EOT, the electrical performance with low gate leakage current of the GaSb MOS capacitors demonstrates the high feasibility of the proposed treatments.

Impact of Channel Orientation on Electrical Properties of Ge p- and n-MOSFETs With 1-nm EOT Al2O3/GeOx/Ge Gate-Stacks Fabricated by Plasma Postoxidation

The impact of surface orientations on electrical characteristics of Ge pand n-channel MOSFETs with ultrathin equivalent oxide thickness Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GeOx/Ge gate-stacks is systematically investigated. It is found that (100), (110), and (111) GeOx/p-Ge metal-oxide-semiconductor (MOS) interfaces have a similar interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) level, but (100) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /n-Ge MOS interfaces exhibit the lowest D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> . As a result, the highest peak mobility is obtained in (110) Ge pMOSFETs for holes and in (100) Ge nMOSFETs for electrons. The higher interface state density is observed inside valence band of Ge for (110) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge MOS interface and inside conduction band of Ge for (110) and (111) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge MOS interfaces, leading to the significant effective mobility reduction in high normal field for (110) Ge pMOSFETs, and (110) and (111) Ge nMOSFETs. It is also confirmed that decrease of plasma oxidation temperature is also effective in reduction of the interface roughness at (100) to (111) GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge interfaces, resulting in clear enhancement of both hole and electron mobility in high normal field region.

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

One of the most critical issues for Ge/III-V MOSFETs is gate insulator formation. In this paper, we focus on viable Ge/III-V MOS gate stack technologies realizing the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). these requirements. As for Ge gate stacks, we present a ultrathin EOT Al2O3/GeOx/Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. (100) Ge pMOSFETs using GeOx/Ge MOS interfaces is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm2/Vs. As for InGaAs gate stacks, we show the impact of Al2O3 inter-layers on interface properties of HfO2/InGaAs MOS interfaces. The 1-nm-thick capacitance equivalent thickness (CET) in the HfO2/Al2O3/InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4e-2 A/cm2.

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation

An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

Two methods of HfO2 nitridation including plasma N2 nitridation and thermal NH3 anneal were studied for ultrathin HfO2 gate dielectrics with &amp;lt;1 nm equivalent oxide thickness (EOT). The detailed nitridation mechanism, nitrogen depth profile, and nitrogen behavior during the anneal process were thoroughly investigated by XPS and SIMS analysis for the two types of nitridation processes at different process conditions. Intermediate metastable nitrogen was observed and found to be important during the plasma nitridation process. For thermal NH3 nitridation, pressure was found to be most critical to control the nitrogen profile while process time and temperature produced second order effects. The physical analyses on the impacts of various process conditions are well correlated to the electrical properties of the films, such as leakage current, EOT, mobility, and transistor bias temperature instability.

High-Field Transport Investigation for 25-nm MOSFETs With 0.64-nm EOT: Intrinsic Performance and Parasitic Effects

Low- and high-field transports are investigated for HfO2-based MOSFETs with ultrathin equivalent oxide thickness (UTEOT) achieved by a remote interface layer (IL) scavenging method. A detailed comparison with a SiON reference demonstrates none of the detrimental effects from HfO2-related Coulomb nor phonon additional scattering on the high-field velocity. Increased surface roughness may reduce the high-field velocity by 20% for the device with the thinnest IL. This is explained by an increase of the backscattering which reduces the ballistic efficiency for the shortest devices . However, the on-state current for UTEOT devices has the best performance at a given high-lateral-field velocity. Therefore, EOT scaling remains a valid tool for ION-performance improvement for CMOS scaling also with new architectures and substrates.

Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS

Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current Igb and gate capacitance Cgg characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12A, and radio frequency-capacitance voltage (RF-CV) technique is used for Cgg measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model Igb and Cgg behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both Igb and Cgg characterization. Impact of Igb and Cgg changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices.

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

High-Mobility Ge pMOSFET With 1-nm EOT $\hbox{Al}_{2} \hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stack Fabricated by Plasma Post Oxidation

An ultrathin equivalent oxide thickness (EOT) Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> / GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge gate stack with a superior GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge metal-oxide-semiconductor (MOS) interface and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) using this gate stack have been fabricated by a plasma post oxidation method. The properties of the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> / Ge MOS interfaces are systemically investigated, and it is revealed that there is a universal relationship between the interface state density ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) at the GeO <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> /Ge interface and the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> interfacial layer thickness. Ge pMOSFETs on a (100) Ge substrate using the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Ge gate stack have been demonstrated with an EOT down to 0.98 nm. It is found that the Ge pMOSFETs exhibit the peak hole mobility values of 515, 466, and 401 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / V·s at an EOT of 1.18, 1.06, and 0.98 nm, respectively, which has much weaker EOT dependence than the trend of the hole mobility values reported so far, because of low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> of the present gate stack in the ultrathin EOT region of ~1 nm.

Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High-$\kappa$ Dielectrics and Si Channel

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this letter, we report that by employing the <formula formulatype="inline"> <tex>$\hbox{La}_{2}\hbox{O}_{3}/ \hbox{SiO}_{x}$</tex></formula> interfacial layer between HfLaO <formula formulatype="inline"><tex>$(\hbox{La} = \hbox{10}\%)$</tex> </formula> high-<formula formulatype="inline"><tex>$\kappa$</tex></formula> and Si channel, the <formula formulatype="inline"><tex>$\hbox{Ta}_{2}\hbox{C}$</tex> </formula> metal-gated n-MOSFETs <formula formulatype="inline"><tex>$V_{T}$</tex> </formula> can be significantly reduced by <formula formulatype="inline"> <tex>$\sim$</tex></formula>350 mV to 0.2 V, satisfying the low- <formula formulatype="inline"> <tex>$V_{T}$</tex></formula> device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness (<formula formulatype="inline"> <tex>$\sim$</tex></formula>1.18 nm) with a low gate leakage (<formula formulatype="inline"> <tex>$J_{G} = \hbox{10}\ \hbox{mA/cm}^{2}$</tex></formula> at 1.1 V), good drive performance (<formula formulatype="inline"><tex>$I_{\rm on} = \hbox{900}\ \mu\hbox{A}/\mu\hbox{m}$ </tex></formula> at <formula formulatype="inline"> <tex>$I_{\rm soff} = \hbox{70}\ \hbox{nA}/\mu\hbox{m}$</tex></formula>), and acceptable positive-bias-temperature-instability reliability. </para>

La Al O 3 gate dielectric with ultrathin equivalent oxide thickness and ultralow leakage current directly deposited on Si substrate

By a careful choice of film deposition conditions, LaAlO3 (LAO) gate dielectric film with equivalent oxide thickness (EOT) of 0.31nm and gate leakage current density (Jg) of 0.1A∕cm2 (at Vfb+1V) has been successfully demonstrated. Elimination of interfacial low-k layer at LAO/Si and reduction of defect density in LAO has been realized through both LAO film deposition at high-temperature (700°C) and subsequent low-temperature (200°C) annealing. By using thermal desorption spectroscopy technique, we find that our process reduces remnant H2O or OH− species in the LAO film, which are responsible for the degradation of EOT and Jg.

Hafnium Titanate bilayer structure multimetal dielectric nMOSCAPs

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bilayer multimetal oxide dielectric has been developed for high-performance CMOS applications. Ultrathin equivalent oxide thickness (/spl sim/8 /spl Aring/) has been achieved with increased effective permittivity (k/spl sim/36). Hysteresis was significantly reduced using the bilayer dielectric. Top TiO/sub 2/ layer was found to induce effective negative charge from the flatband voltage shift. Leakage current characteristic was slightly higher than control HfO/sub 2/, and this is believed to be due to the lower band offset of TiO/sub 2/. However, the interface state density of this bilayer structure was found to be similar to that of HfO/sub 2/ MOSCAP because the bottom layer is HfO/sub 2/. These results demonstrate the feasibility of new multimetal dielectric application for future CMOS technology.