Ultra-high Integration Density Research Articles

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

First-Principles Prediction of High and Low Resistance States in Ta/h-BN/Ta Atomristor.

Two-dimensional (2D) materials have received significant attention for their potential use in next-generation electronics, particularly in nonvolatile memory and neuromorphic computing. This is due to their simple metal-insulator-metal (MIM) sandwiched structure, excellent switching performance, high-density capability, and low power consumption. In this work, using comprehensive material simulations and device modeling, the thinnest monolayer hexagonal boron nitride (h-BN) atomristor is studied by using a MIM configuration with Ta electrodes. Our first-principles calculations predicted both a high resistance state (HRS) and a low resistance state (LRS) in this device. We observed that the presence of van der Waals (vdW) gaps between the Ta electrodes and monolayer h-BN with a boron vacancy (VB) contributes to the HRS. The combination of metal electrode contact and the adsorption of Ta atoms onto a single VB defect (TaB) can alter the interface barrier between the electrode and dielectric layer, as well as create band gap states within the band gap of monolayer h-BN. These band gap states can shorten the effective tunneling path for electron transport from the left electrode to the right electrode, resulting in an increase in the current transmission coefficient of the LRS. This resistive switching mechanism in monolayer h-BN atomristors can serve as a theoretical reference for device design and optimization, making them promising for the development of atomristor technology with ultra-high integration density and ultra-low power consumption.

Gate-Tunable Spin Seebeck Effect and Pure Spin Current Generation in Molecular Junctions Based on Bipolar Magnetic Molecules.

Generating pure spin currents is very desirable in spintronics, as it provides a promising way to substantially reduce Joule heating and achieve ultrahigh integration density. However, to date, most spintronic devices exhibit spin currents that are accompanied by charge currents. The generation of pure spin currents on the nanoscale, particularly at the single-molecule level, remains challenging. Here, we propose that by exploiting our recently reported bipolar magnetic molecules (BMMs) as the core component of single-molecule devices, where the highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) come from different spin channels, the generation of pure spin currents can be easily realized via the spin Seebeck effect (SSE) with applied temperature gradient. Moreover, the spin Seebeck coefficient can be modulated over a wide range by applying an external gate voltage. The proposal is verified through first-principles calculations on two BMM-based molecular junctions.

Low-loss chip-scale programmable silicon photonic processor

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications, such as lidar, radar, and artificial intelligence. Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility, and thus makes it possible to develop large-scale programmable optical signal processors. The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors. In this paper, we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches. The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers (MZCs), four Ge/Si photodetectors, four channels of thermally-tunable optical delaylines. Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step. Particularly, these waveguide spirals used here are designed to be as wide as 2 µm, enabling an ultralow propagation loss of 0.28 dB/cm. Meanwhile, these MZCs and MZSs are designed with 2-µm-wide arm waveguides, and thus the random phase errors in the MZC/MZS arms are negligible, in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly. Finally, this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities, including tunable time-delay, microwave photonic beamforming, arbitrary optical signal filtering, and arbitrary waveform generation.

Atomically Thin Synapse Networks on Van Der Waals Photo-Memtransistors.

A new type of atomically thin synaptic network on van der Waals (vdW) heterostructures is reported, where each ultrasmall cell (≈2nm thick) built with trilayer WS2 semiconductor acts as a gate-tunable photoactive synapse, i.e., a photo-memtransistor. A train of UV pulses onto the WS2 memristor generates dopants in atomic-level precision by direct light-lattice interactions, which, along with the gate tunability, leads to the accurate modulation of the channel conductance for potentiation and depression of the synaptic cells. Such synaptic dynamics can be explained by a parallel atomistic resistor network model. In addition, it is shown that such a device scheme can generally be realized in other 2D vdW semiconductors, such as MoS2 , MoSe2 , MoTe2 , and WSe2 . Demonstration of these atomically thin photo-memtransistor arrays, where the synaptic weights can be tuned for the atomistic defect density, provides implications for a new type of artificial neural networks for parallel matrix computations with an ultrahigh integration density.

Three-Dimensional Perovskite Nanopixels for Ultrahigh-Resolution Color Displays and Multilevel Anticounterfeiting.

Hybrid perovskites are emerging as a promising, high-performance luminescent material; however, the technological challenges associated with generating high-resolution, free-form perovskite structures remain unresolved, limiting innovation in optoelectronic devices. Here, we report nanoscale three-dimensional (3D) printing of colored perovskite pixels with programmed dimensions, placements, and emission characteristics. Notably, a meniscus comprising femtoliters of ink is used to guide a highly confined, out-of-plane crystallization process, which generates 3D red, green, and blue (RGB) perovskite nanopixels with ultrahigh integration density. We show that the 3D form of these nanopixels enhances their emission brightness without sacrificing their lateral resolution, thereby enabling the fabrication of high-resolution displays with improved brightness. Furthermore, 3D pixels can store and encode additional information into their vertical heights, providing multilevel security against counterfeiting. The proof-of-concept experiments demonstrate the potential of 3D printing to become a platform for the manufacture of smart, high-performance photonic devices without design restrictions.

LiNbO3 waveguide with embedded Ag nanowire and 3L MoS2 for strong light confinement and ultra-long propagation length in the visible spectral range.

A vertical slot LiNbO3 waveguide with an Ag nanowire and 3L MoS2 embedded in the low-refractive index slot region is proposed for the purpose of improving light confinement. We find that the proposed waveguide has a novel dielectric based plasmonic mode, where local light field is enhanced by the Ag nanowire. The mode exhibits an extremely large figure of merit (FoM) of 6.5×106, one order of magnitude larger than that the largest FoM of any plasmonic waveguide reported in the literature to date. The waveguide also has an extremely long propagation length of 84 cm in the visible wavelength at 680 nm. Furthermore, the waveguide has a low sub-micro bending loss and can be directly connected to all-dielectric waveguides with an extremely low coupling loss. The proposed vertical slot LiNbO3 waveguide is a promising candidate for the realization of ultrahigh integration density tunable circuits in the visible spectral range.

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density

Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential integration density benefits of M3D circuits also may not be fully realized by the large area skews between different layers within standard cells. In this paper, ultra-high density and robust M3D static random-access memory (SRAM) cells are proposed for tolerance to the removal of m-CNs. By minimizing the skew and area of each device layer, the 16Kibit memory arrays with the proposed SRAM cells enhance the integration density by up to 82.92% as compared to the carbon-based traditional 2D and previously published M3D memory arrays. While achieving high functional yield and maintaining robust read/write operations, the proposed SRAM circuits enhance the overall electrical quality by up to 27.41x as compared to the alternative 2D and M3D memory arrays.

Electrical Broad Tuning of Plasmonic Color Filter Employing an Asymmetric-Lattice Nanohole Array of Metasurface Controlled by Polarization Rotator

Wide range of color change in nanohole array structure on a metal film have been successfully demonstrated using asymmetric-lattice design of nanoholes and an electrically switching polarization rotator. Recently, some studies have been reported that various color states were obtained in a single unit cell structure using extraordinary optical transmission (EOT) of nanopatterned structure, which could be one of the most important solutions for achieving ultrahigh integration density in optoelectronic devices. However, because they used the interfacial refractive index or dielectric constant as controlling factors for the color tuning, they were not capable of inducing a changeable range of color with different primary color states. To overcome this limitation, in this study, an asymmetric-lattice nanohole array design was integrated with an electrically controlled polarization rotator, employing a twisted nematic (TN) liquid crystal (LC). This simple structure of nanohole arrays with a rectangular lattice...

Ultrafast metal-insulator-multi-wall carbon nanotube tunneling diode employing asymmetrical structure effect

Ultra-fast diode structures based on non-semiconductive materials employing tunneling mechanism have been investigated. Applying the structurally asymmetric effect of multi-wall carbon nanotube (MWCNT) to a vertical metal-insulator-MWCNT (MIC) tunneling diode structure, the ‘on-off’ ratio (∼104) and the current density (38.2 MA/cm2) are drastically enhanced compared to those of conventional metal-insulator-metal (MIM) tunneling diodes. The electrical characteristics are stable up to 423 K. Experimentally, rectifying performance of the MIC diode is good up to 10 MHz and the cut-off frequency of the MIC diode is estimated to be 6.47 THz. The growth process of MWCNT is more controllable for the number and the position than that of SWCNT. Therefore, it has a high probability of realization. The vertically aligned single MWCNT design can guarantee an ultra-high integration density, as well. Therefore, the MIC diode can be applied to various high frequency applications, such as communication devices, high speed electrical switches, and high performance control process units (CPUs), or other new concept devices.

Utilization of Field Enhancement in Plasmonic Waveguides for Subwavelength Light-Guiding, Polarization Handling, Heating, and Optical Sensing.

Plasmonic nanostructures have attracted intensive attention for many applications in recent years because of the field enhancement at the metal/dielectric interface. First, this strong field enhancement makes it possible to break the diffraction limit and enable subwavelength optical waveguiding, which is desired for nanophotonic integrated circuits with ultra-high integration density. Second, the field enhancement in plasmonic nanostructures occurs only for the polarization mode whose electric field is perpendicular to the metal/dielectric interface, and thus the strong birefringence is beneficial for realizing ultra-small polarization-sensitive/selective devices, including polarization beam splitters, and polarizers. Third, plasmonic nanostructures provide an excellent platform of merging electronics and photonics for some applications, e.g., thermal tuning, photo-thermal detection, etc. Finally, the field enhancement at the metal/dielectric interface helps a lot to realize optical sensors with high sensitivity when introducing plasmonic nanostrutures. In this paper, we give a review for recent progresses on the utilization of field enhancement in plasmonic nanostructures for these applications, e.g., waveguiding, polarization handling, heating, as well as optical sensing.

Associative Memory Function Found on Phase-Change Nanoscale Device

Associative memory, considered as the ability to link unrelated objects, is the most appealing behaviour found in both biological and artificial neural networks. Here we for the first time proposed a three terminal phase-change based nanoscale device where associative memory can be theoretically achieved according to the developed electro-thermal model. Compared with the conventional neural networks circuit, the designed device allows for an exemption from a large number of circuit elements, and thus exhibits an exciting potential for ultra-high integration density and super-fast response speed. The simulation results opens up a novel route to imitate the complex mechanism of the biological neural networks, thus rendering phase-change materials a promising contender for the key components in next-generation neuromorphic system. Keywords: Associative memory, model, neural, phase-change.

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability.

Towards neuromorphic electronics: Memristors on foldable silicon fabric

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex׳s folded pattern for ultra-compact design.

High Growth Yield of Single Multiwall Carbon Nanotube With Different Length Effect

Vertically aligned single multiwalled carbon nanotube (MWCNT) is quite an interesting nanostructure due to its high probability of nanodevice realization with an ultrahigh integration density. Although ~200 nm catalyst diameter size and plasma-enhanced chemical vapor deposition (PECVD) method have been known as key parameters to grow a single MWCNT, the details and the phenomenon of below 200 nm catalyst size have not been studied or published well. Here, we report the details of catalyst size effect below 200 nm. One-hundred-nanometer diameter Ni catalyst on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer shows 95% yield of single MWCNT growth. Surface roughness of substrate makes a large deviation in the yield and the critical catalyst size for single MWCNT. The various catalyst sizes result in the different growth rate of carbon nanotube (CNT) at the same growth condition. The change of diffusion surface area induces such a difference. From the results, single MWCNTs with various lengths are successfully grown on the same substrate by a one-step growth process.

A Hybrid Plasmonic Waveguide for the Propagation of Surface Plasmon Polariton at 1.55 μm on SOI Substrate

A hybrid plasmonic waveguide (HPW) has been numerically investigated, based on silicon-on-insulator (SOI) structure near the telecom wavelength λ = 1550 nm using the finite-element method. The HPW consists of metal cap placed on SOI rib, which has a trench with a semicircle interface at the bottom of the trench. With the proper choice of waveguide sizes, our proposed HPW can support hybrid long-range surface plasmon which have strong mode confinement A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> /A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ≅ 0.0035-0.035 and long propagation length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> > 525 μm) simultaneously. In addition, for the proposed HPW, the calculated coupling length for two parallel identical waveguides which is separated by distance d = 250 nm is approximately 1.3 μm, which is very helpful in realizing photonic integration circuits with ultrahigh integration density.

Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory

Nano/molecular technologies have emerged as the potential fabrics for building future integrated systems. However, due to the imperfect fabrication process, these extremely scaled devices are vulnerable to a large number of defects and transient faults. Memory systems, which are the primary application targeted by these technologies, are particularly exposed to this problem due to the ultra-high integration density and elevated error sensitivity. In this article, we propose a defect-tolerant technique, referred to as hybrid redundancy allocation , for the design of molecular crossbar memory systems. By using soft redundancy (runtime exploitation of memory spatial/temporal locality) in combination with hardware redundancy (spare memory cells), the proposed technique can achieve better error management at a low cost as compared with conventional techniques. Simulation results demonstrate the significant improvement in defect tolerance, efficiency, and scalability of the proposed technique.

Physical Modeling of the Capacitance and Capacitive Coupling Noise of Through-Oxide Vias in FDSOI-Based Ultra-High Density 3-D ICs

Fully depleted silicon-on-insulator (FDSOI) technology boosts the opportunity to make 3-D ICs with ultrahigh integration density, due to the short and tiny through-oxide vias (TOVs), which are made after removing the entire silicon under the buried-oxide layer. This work, for the first time, develops compact physical models for the capacitance of the TOV and the coupling capacitance between the TOV and active regions in the presence of periodical power/ground lines, from fundamental electrostatic considerations. Calculation results from the models show good agreement with the simulation results from a full-3-D capacitance solver. The models are further used to analyze the threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) variation in the FDSOI MOSFETs. The TOV in FDSOI and the through-silicon via (TSV) in bulk-CMOS-based 3-D ICs are finally compared in terms of the self-impedance as well as their impact on MOSFET <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation through capacitive noise coupling. These results provide important insights to TOV/TSV design and optimization in emerging 3-D ICs.

Low-loss hybrid plasmonic waveguide with double low-index nano-slots

A hybrid plasmonic waveguide with double low-index nano-slots is introduced. The fabrication is simple and compatible with the standard processes for SOI wafers. The theoretical investigation shows that the present hybrid plasmonic waveguide has a low loss and consequently a relatively long propagation distance (at the order of several tens of lambda). For TE polarization, there is a strong field enhancement in the double nano-slots. More power is confined in the low-index nano-slots for a smaller core width. For a 50 nm-wide hybrid plasmonic waveguide with double 10 nm-wide slots, the power confinement factor in the nano-slots is as high as 85% and the effective area is as small as 0.007 microm(2) at 1550 nm. Consequently, the power density in the nano-slots becomes very high, e.g., >120 microm(-2), which is very desired for many applications. For the present hybrid plasmonic waveguide, the lateral dimension could be less than 50 nm and the calculated decoupled separation for two parallel identical waveguides is only 0.62 microm, which is helpful to realize photonic integration circuits with ultra-high integration density.

Two-bit ferroelectric field-effect transistor memories assembled on individual nanotubes

Carbon nanotube (CNT) ferroelectric field-effect transistors (FeFETs) with well-definedmemory switch behaviors are promising for nonvolatile, nondestructive read-out (NDRO)memory operation and ultralow power consumption. Here, we report two-bit CNT-FeFETmemories by assembling two top gates on individual nanotubes coated with ferroelectric thinfilms. Each bit of the nanotube transistor memory exhibits a controllable memory switchingbehavior induced by the reversible remnant polarization of the ferroelectric films, and itsNDRO operation is demonstrated. The low driving voltage of 2 V, high carrier mobility over1000 cm2 V−1 s−1, and potential ultrahigh integration density over200 Gbit inch−2 of the two-bit FeFET memory are highlighted in this paper.