Ultrathin Body Silicon Research Articles

Crystalline Silicon Spalling as a Direct Application of Temperature Effect on Semiconductors’ Indentation

Kerf-less removal of surface layers of photovoltaic materials including silicon is an emerging technology by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material; then, the controlled removal of a continuous surface layer can be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer, introducing a crack near the edge of the substrate, and mechanically guiding the crack as a single fracture front across the surface. However, spalling Si(100) at 300 K (room temperature RT) introduced many cracks and rough regions within the spalled layer. These mechanical issues make it difficult to process these layers of Si(100) for PV, and in other advanced applications, Si does not undergo phase transformations at 77 K (Liquid Nitrogen Temperature, LNT); based on this fact, spalling of Si(100) has been carried out. Spalling of Si(100) at LNT improved material quality for further designed applications. Mechanical flexibility is achieved by employing controlled spalling technology, enabling the large-area transfer of ultrathin body silicon devices to a plastic substrate at room temperature.

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress

We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stress in [110] direction applied to a (001) film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the dependence of the non-parabolicity parameter on film thickness and strain. The influence of the subband structure modification on the mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. It is shown that an increase of subband non-parabolicity in thin films with strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values.

Performance Evaluation and Device Physics Investigation of Negative-Capacitance MOSFETs Based on Ultrathin Body Silicon and Monolayer MoS2

The proposition of integrating the 2-D materials and ferroelectric negative-capacitance MOSFETs (NCFETs) was expected to have excellent steep slope ${I}$ – ${V}$ characteristics due to the combined advantages of both ultrathin body channel material and negative-capacitance effect. Recent experiments demonstrated the excellent steep slope features of 2-D material NCFETs. Therefore, it was important to understand the device physics of this characteristic, its performance projection, and the benchmark with NCFETs based on conventional Group IV materials. In this article, we conducted a computational study of 2-D material NCFETs based on MoS2 under the nonequilibrium Green’s function (NEGF)-Poisson self-consistent scheme with free-Gibbs energy calculation to judge the operating path in polarization–electric field (P–E) relation. Monolayer MoS2 (1L-MoS2) was chosen as channel material while various thickness of ultrathin body silicon (UTB-Si) for benchmark purpose. The results showed an excellent average subthreshold slope (SS) of ~25 mV/dec in 1L-MoS2 NCFETs compared to ~32 mV/dec of the UTB-Si counterparts. It was found that the steep-slope features in 1L-MoS2 NCFETs could be attributed to the more optimized capacitance matching in 1L-MoS2 NCFETs and tunneling currents at the subthreshold region.

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study

The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground plane (GP) inside a high-K buried oxide (BOX). Using calibrated 2-D simulations, it is demonstrated that a SOI-JLFET with the ground plane placed at a shallow depth within the high-K dielectric BOX not only assists in the efficient volume depletion of the channel but also results in a drastically reduced L-BTBT action. The efficient volume depletion, therefore, relaxes the constraints of ultra-thin silicon body for SOI-JLFET and circumvents the need of complex device architectures for achieving the same. Also, the depletion of the drain and source regions jointly results in a drastically reduced L-BTBT induced parasitic BJT action in the OFF-state and in the negative bias regime. The simultaneous suppression of both the leakage mechanisms results in an overall leakage current reduction leading to a significant ON-state to OFF-state current ratio ( $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}})$ of 106 and 105 even at the scaled gate length of 10 nm and 7 nm, respectively. Additionally, a significant reduction in the drain-induced barrier lowering and threshold voltage roll-off is observed in a GP-JLFET. The GP-JLFET also exhibits an appreciable $\text{I}_{\mathrm {ON}}/\text{I}_{\mathrm {OFF}}$ ratio under the influence of process variations of doping and film thickness without any considerable degradation in the performance. Thus, the suppressed leakage mechanisms and short channel effects in the proposed device provide an incentive for realizing the SOI-JLFETs in the sub-10 nm regime for low power and low-leakage applications.

Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed.

Quantum Transport Study of Si Ultrathin-Body Double-Gate pMOSFETs: <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math> </inline-formula>, <inline-formula> <tex-math notation="LaTeX">${C}$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math> </inline-formula>, Energy Delay, and Parasitic Effects

A comprehensive quantum transport study of ultrathin-body silicon double-gate pMOSFETs with gate length ${L}_{\textsf {g}}= \textsf {14}$ , 10, and 7 nm is performed by in-house developed nonequilibrium Green’s function solver employing the six-band ${k} \cdot {p}$ Hamiltonian. The effects of channel length, body thickness, as well as confinement and transport crystal orientations are studied systematically. Both ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics are analyzed in this paper. Furthermore, the CMOS performance benchmarking results, such as switching delay, energy consumption, and their product, are calculated with the influence of parasitic resistances and capacitances treated in an appropriate way. It is found that the crystal orientation effect on drive current is significant at both long and short channel lengths, while its effect on effective capacitance is more observable at ${L}_{\textsf {g}} = \textsf {7}$ nm. The drive current at ${L}_{\textsf {g}} = \textsf {14}$ nm and ${L}_{\textsf {g}} = \textsf {7}$ nm can be well explained by average ballistic hole velocity and source-to-drain tunneling ratio, respectively. Meanwhile, the effective capacitance is not only determined by the density of states but also affected by the distribution of holes in the confined direction. Both intrinsic and extrinsic performance assessments suggest that (001)/[100] and (110)/[001] are the optimal confinement/transport crystal orientation configurations at ${L}_{\textsf {g}}= \textsf {7}$ nm, while ${(}\textsf {110}{)}/[\overline {1}\textsf {10}]$ and ${(}\textsf {110})/[\overline {1}\textsf {11}]$ are the best choices at longer gate lengths. As ${L}_{\textsf {g}}$ shrinks, both intrinsic and extrinsic performances will be better at a scaled body thickness.

Extrinsic gate capacitance compact model for UTBB MOSFETs

Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.

A dielectrically modulated electrically doped tunnel FET for application of label free biosensor

The fabrication challenges and cost of nanoscale devices have been a major concern in the field of label free biosensor. Therefore, to overcome these issues, we report for the first time a dielectrically modulated electrically doped tunnel field-effect transistor (DM-EDTFET) as a biosensor for label free detection. For this purpose, n+ drain and p+ source regions in proposed device are induced by considering polarity bias of PG-1 = +1.2 V and PG-2 = −1.2, respectively over the ultra-thin silicon body. The proposed structure is immune against doping control issues, avoids thermal budget and fabrication complexity as compared to its counterpart TFET. In DM-EDTFET, a nanogap cavity embedded within the gate dielectric is formed by etching the selected portion of gate dielectric layer towards the source side for sensing the biomolecules. The sensing ability of DM-EDTFET has been analysed in terms of variation in dielectric constant and charge density of biomolecules, and device geometry parameters at different bias conditions. To analyse the relative sensitivity, proposed DM-EDTFET is compared with MOSFET based biosensor in terms of sensing parameters. From these results, DM-EDTFET provides superior results in terms of sensitivity as compared to MOSFET based biosensor. Hence, the proposed DM-EDTFET biosensor can be a promising candidate for the development of future sensing bio-equipments.

Experimental $I$ – $V(T)$ and $C$ – $V$ Analysis of Si Planar p-TFETs on Ultrathin Body

We present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance–voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of $C_{\mathrm {gs}}$ to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance $C_{\mathrm {gd}}$ . This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits.

Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges

This paper is a unique attempt to identify the zero-temperature-coefficient (ZTC) point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a biasing point i.e. ZTC bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on various performance metrics like on current (Ion), off current (Ioff), on-off current ratio (Ion/Ioff), transconductance (gm), output conductance (gd), intrinsic gain (AV) and cut off frequency (fT) is also subjected to extensive analysis. The variation of ZTC point for transconductance (ZTCgm) and drain current (ZTCIDS) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.

Extremely Flexible Nanoscale Ultrathin Body Silicon Integrated Circuits on Plastic

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm–5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (Vth) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φc) saturates to Φc(sat), and analyze the effects of oxide thickness (tox) and substrate doping (NA) variations on Vth. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed Vth definition, electrically corresponds to a condition where the inversion layer capacitance (Cinv) is equal to the oxide capacitance (Cox) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria Cinv=Cox is proposed to compute Φc(sat), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (“x”) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film.

Quantum confinement effects and source-to-drain tunneling in ultra-scaled double-gate silicon n-MOSFETs

By using the linear combination of bulk band (LCBB) method incorporated with the top of the barrier splitting (TBS) model, we present a comprehensive study on the quantum confinement effects and the source-to-drain tunneling in the ultra-scaled double-gate (DG) metal—oxide—semiconductor field-effect transistors (MOSFETs). A critical body thickness value of 5 nm is found, below which severe valley splittings among different X valleys for the occupied charge density and the current contributions occur in ultra-thin silicon body structures. It is also found that the tunneling current could be nearly 100% with an ultra-scaled channel length. Different from the previous simulation results, it is found that the source-to-drain tunneling could be effectively suppressed in the ultra-thin body thickness (2.0 nm and below) by the quantum confinement and the tunneling could be suppressed down to below 5% when the channel length approaches 16 nm regardless of the body thickness.

Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs

This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL.

Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs

The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical DC parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.

Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model – Part 1 analytical consideration and strain-induced valley splitting

Multi-gate FinFETs and ultra-thin silicon body SOI FETs are considered as perfect candidates for future technology nodes. Strong size quantization leads to a formation of quasi-two-dimensional subbands in carrier systems within thin silicon films. The employed Hensel–Hasegawa–Nakayama k·p Hamiltonian accurately describes the bulk structure up to the energies of 0.5–0.8eV and includes a shear strain component. Shear strain is responsible for effective mass modification and is therefore an important source of the electron mobility enhancement in ultra-thin silicon films. The influence of shear strain on the subband structure in thin silicon films is investigated.

Uniaxial Stress Dependence of Electrical Properties of Ulrathin Ballistic P-Type Silicon Nanotransistor

. In this paper, in order to determine whether the ballistic current enhancement saturates at very high stress level or can be further improved, the effect of uniaxial stress on the ballistic transport of the double-gated, ultrathin-body p-type silicon nanotransistor is investigated using a self-consistent device simulator, which combines the stress-dependent six-band k.p model and a semiclassical top-of-the-barrier ballistic transport model. Based on a semi-continuum atomistic lattice model, the size-dependent elastic constant correction has been for the first time coupled into this simulator. Our results presented here indicate uniaxial compressive stress at moderate levels improves ballistic performance by about 85% while uniaxial tensile stress slightly reduces ballistic drive current. Interestingly, higher compressively strained channel does not offer higher drive current. Although significant variations in the size-dependent elastic constants are found, the ballistic current shows only a small decrease after considering the elastic constant correction. Furthermore, the competition of injection velocity and carrier density related to hole effective masses is found to play a critical role in determining the performance of the nanotransistors.

Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress

Mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stress in [110] direction applied to a (001) silicon film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the non-parabolicity dependence on film thickness and on strain. Dependence of the non-parabolicity parameter on both film thickness and strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values.