Ultra-thin Gate Oxide Reliability Research Articles

Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides

The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm.

Reliability of ultrathin gate oxides for ULSI devices

Abstract Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. This paper reviews the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies. Issues including gate leakage current, time-dependent dielectric breakdown, poly-gate depletion, boron penetration, and plasma process-induced damage will be addressed. Several techniques such as nitrided oxide and alternative processes, which are proposed to improve gate oxide reliabilities, are also discussed.

Influence of Native Oxides on the Reliability of Ultrathin Gate Oxide

The influence of wet cleaning processes, such as the SC-1 and H2O2 processes, on the time dependent dielectric breakdown (TDDB) of ultrathin gate oxide was investigated. A large difference in the reliability by wet cleaning processes was observed, especially when an electrode is an anode. The reliability of the gate oxide by the H2O2 process was worse than SC-1. It was found by Fourier transformed infrared attenuated total reflection (FT-IR-ATR) analysis that the amount of structural imperfection of native oxides formed in H2O2 was larger than SC-1. Since stress-induced positive charges which affect the TDDB properties are generated near the anode- side oxide interface, a large amount of structural imperfection in the native oxides formed in H2O2 probably results in a defective thermal oxide surface, leading to an increase in the generation and trapping of positive charge.

Ultra thin gate oxide reliability enhanced by carbon contamination free process

In this paper, we have demonstrated that carbon contamination caused by a wafer exposure to clean room air induces the degradation of a gate oxide reliability, and we have improved a gate oxide reliability by using a closed system, where the oxidation is followed by an in-situ phosphorus doped polycrystalline Si (poly-Si) gate formation in the same furnace. Furthermore, in opened system, we have demonstrated the removal of the carbon contamination by using only O 3 gas ambient and O 3 gas ambient combined with IR lamp irradiation.

Reliability of Ultra-Thin Gate Oxide Below 3 nm in the Direct Tunneling Regime

Cluster tool furnace technology was used to control the growth of extremely uniform ultra-thin 1.5 nm to 3 nm SiO2 layers on Si. The transition from Fowler-Nordheim tunneling to direct tunneling electron injection for sub-3-nm oxide poly-Si gate metal-oxide-silicon capacitor structures is described and the influence on the oxide reliability is discussed. It is shown that oxide breakdown can still occur at low voltages in the direct tunneling regime under the condition of electron injection from the poly-Si gate. Soft breakdown of these ultra-thin oxide layers, accompanied by the occurrence of complex fluctuations in the direct tunneling current, is demonstrated. Using this as the definition of sub-3-nm oxide breakdown, it is shown for the first time that the time to dielectric breakdown of the sub-3-nm gate oxide in the direct tunneling regime is determined by the electrical field strength in the oxide similarly to the case of the sub-3-nm dielectric breakdown in Fowler-Nordheim tunnel stressing.

Dependence of Reliability of Ultrathin Mos Gate Oxides on the Fermi Level Positions at Gate and Substrate

ABSTRACTWe demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.

Effect of BF2 implantation on ultrathin gate oxide reliability

BF2 implantation is widely used to form P wells, adjust channel threshold voltage, and reduce short channel effects. In this letter, we study effect of BF2 implantation on ultrathin gate oxide reliability. It has been found that BF2 implantation into Si substrate causes degradation of gate oxide reliability in the ultrathin oxide thickness regime. N2O oxide can be used to reduce degradation caused by the implantation and improve gate oxide reliability.

Soft breakdown of ultra-thin gate oxide layers

The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Effect of Growth Conditions on the Reliability of Ultrathin MOS Gate Oxides

AbstractIn this work we demonstrate that in MOS devices the reliability of ultrathin (< 100Å) gate oxide is a strong function of growth conditions, such as, temperature and the growth rate. In addition, for constant current gate injection the degradation of SiO2 is enhanced as the thickness is reduced. We attribute this to physical stress in SiO2 resulting from the growth process. The degradation is always more for those growth conditions which result in higher physical stress in SiO2. Higher temperatures and slower oxidation rates allow stress relaxation through viscous flow and hence result in SiO2 of better reliability. We also found that for constant current stressing, the interface damage is more at the collecting electrode than at the injecting electrode. ΔDit (stress induced interface state generation) can be reduced after a high temperature Ar post anneal after the gate oxide growth.