Ultra-thin Body Research Articles

Influence of Supply Voltage and Body Biasing on Single-Event Upsets and Single-Event Transients in UTBB FD-SOI

In this article, we present the effects of voltage scaling and forward body biasing (FBB) on single-event effect sensitivity of a 28-nm ultra-thin body and box (UTBB) fully depleted silicon on insulator (FD-SOI) technology. Heavy-ion irradiation was performed for single-event upset (SEU) and single-event transient (SET) sensitivity assessment on characterization test chips under three supply voltages, with and without back-gate voltage application. Measurements show a steady SEU sensitivity for any supply voltage across the two FBB configurations, whereas SET sensitivity is diminished under FBB. SPICE and TCAD mixed-mode simulations were run to assess the contribution of electrical factors as well as charge extraction mechanisms. While drive strength is increased under FBB, the bipolar amplification plays an important role in sensitivity at low linear energy transfers (LETs).

Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material

A comparison between cylindrical Gate All Around Nano Wire Field Effect Transistor (GAA NWFET) and a cylindrical Gate All Around Nano Wire Multi Bridge Channel Field Effect Transistor (GAA NWMBCFET) for a gate length of 35 and 5 nm has been carried out in this work. The Nanowire device was converted to a Nanowire MBCFET device by incorporating four channels in the cylindrical structure. The Current–Voltage (I-V) characteristics were thus plotted for both the devices where Silicon Carbide (SiC) is used as a material for source and drain regions for GAA NWMBCFET to increase the performance. The inclusion of a multi bridge channel and SiC in the device increase the current drive because of the Ultra-Thin Body (UTB) and vertically created stress. Due to the associative functionality of the multi bridge channel and SiC, the 5 nm gate length of Cylindrical GAA NWMBCFET achieves 75% of the drain current obtained in the 35 nm gate length Cylindrical GAA NWFET. Additionally, the electron mobility is evaluated, and Subthreshold Swing (SS) is also reported.

Floating Body DRAM with Body Raised and Source/Drain Separation

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Benchmarking monolayer MoS2 and WS2 field-effect transistors

Here we benchmark device-to-device variation in field-effect transistors (FETs) based on monolayer MoS2 and WS2 films grown using metal-organic chemical vapor deposition process. Our study involves 230 MoS2 FETs and 160 WS2 FETs with channel lengths ranging from 5 μm down to 100 nm. We use statistical measures to evaluate key FET performance indicators for benchmarking these two-dimensional (2D) transition metal dichalcogenide (TMD) monolayers against existing literature as well as ultra-thin body Si FETs. Our results show consistent performance of 2D FETs across 1 × 1 cm2 chips owing to high quality and uniform growth of these TMDs followed by clean transfer onto device substrates. We are able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. Our experimental demonstrations confirm the technological viability of 2D FETs in future integrated circuits.

Proposal and Experimental Demonstration of Ultrathin-Body (111) InAs-On-Insulator nMOSFETs With L Valley Conduction

Ultrathin-body (UTB) (111) InAs-On-Insulator (InAs-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) are proposed as a new technology booster using the L valley conduction in III–V channels. The performance of the conventional UTB III–V nMOSFETs is limited by the essential band features of the $\Gamma $ valley conduction such as the low density of states, resulting in low inversion capacitance, and the light effective mass ${m}_{z}$ along the confinement direction, resulting in strong thickness fluctuation scattering. The strong confinement of electrons by a combination of (111) surface orientation and UTB InAs-OI structures is expected to transfer the electrons into the L valley with much heavier ${m}_{z}$ than in the $\Gamma $ valley, leading to higher semiconductor capacitance and suppression of thickness fluctuation scattering. We also experimentally demonstrate the UTB (111) InAs-OI nMOSFETs operation with thinning the InAs channels down to 3 nm, realized by the smart-cut and digital etching process. Channel thickness scaling improves both the OFF- and ON-currents by expansion of the effective bandgap. It is shown that the measured mobility increases with decreasing InAs-OI thickness from 4.8 to 4.4 nm, which is attributable to the increase in the electron occupancy in the L valley.

Electric Field-Induced Permittivity Enhancement in Negative-Capacitance FET

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap.

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

WS2 Film by Sputtering and Sulfur-Vapor Annealing, and its pMISFET With TiN/HfO2 Top-Gate Stack, TiN Bottom Contact, and Ultra-Thin Body and Box

A layered polycrystalline WS2 film is formed by radio-frequency (RF) magnetron sputtering and sulfur-vapor annealing (SVA). Its pMISFET is successfully demonstrated with TiN/HfO2 top-gate stack, TiN contact, and ultra-thin body and box technologies. A WS2 film with a (002) plane is formed parallel to a substrate surface using RF magnetron sputtering, and its crystallinity is drastically enhanced by the SVA. I–V characteristics with p-type operation are confirmed in WS2 MISFETs with a maximum field effect mobility of 1.5 × 10-2 cmV-1s-1. Therefore, our film-formation method is a promising candidate for pMOSFETs in CMOS circuits.

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented GOI nMOSFET has been demonstrated with a reasonable ON/OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> . However, degradation in the effective electron mobility and subthreshold swing (SS) of the (111) GOI nMOSFETs with decreasing the GOI thickness ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOI</sub> ) was observed. Raman analyses and electrical characteristics of GOI nMOSFET under back-gate operation has suggested that a high interface state density at (111) GOI/buried oxide interfaces as well as low GOI film quality near the back interfaces can be an origin of this degradation of the electrical properties with thin body channels.

Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

High-current MoS2 transistors with non-planar gate configuration

The ever-decreasing size of transistors requires effectively electrostatic control over ultra-thin semiconductor body. Rational design of the gate configuration can fully persevere the intrinsic property of two-dimensional (2D) semiconductors. Here we design and demonstrate a 2D MoS2 transistor with omega-shaped gate, in which the local gate coupling is enhanced by the non-planar geometry. The omega-shaped non-planar transistors exhibit a high current of 0.89 A/μm and transconductance of 32.7 μS/μm. The high performance and desirable current saturation promise the construction of robust logic gate. The inverters show a voltage gain of 26.6 and an ideal total margin nearly 89%. We also assemble NOT-AND (NAND) gate on an individual MoS2 flake, and the constructed NAND gate demonstrates the universal functionality of the transistors as well. This work provides an alternative strategy to fully take the advantages of 2D materials for high-performance field-effect transistors.

Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress

We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stress in [110] direction applied to a (001) film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the dependence of the non-parabolicity parameter on film thickness and strain. The influence of the subband structure modification on the mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. It is shown that an increase of subband non-parabolicity in thin films with strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values.

Analytical Model for Interface Traps-Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface traps and short channel effects-dependent back gate capability in the UTBB FDSOI device are proposed. The developed model allows the accurate assessment of body factor ( $\gamma $ ) with the dependence of front/back interface trap density in the ultrascaled FDSOI device, taking the impact of gate area scaling as well as quantum effects into account. It also facilitates the evaluation of back bias effectiveness variability induced by interface traps and benefits the dynamic threshold voltage strategy in terms of adaptive back-biasing for performance optimization, which is consistent with 3-D device simulations and measurements. Moreover, the results confirm that $\gamma $ variability follows Pelgrom’s rule.

Synergy of solid loading and printability of ceramic paste for optimized properties of alumina via stereolithography-based 3D printing

The challenges associated with stereolithography-based ceramic additive manufacturing using high solid loading pastes are related to the printability of ultrathin layers and complex green bodies without auxiliary support structures directly underneath. In order to develop the strategy of conformal contactless support during additive manufacturing, the printability of alumina ceramic paste with a variety of solid loading, along with mechanical properties of the sintered parts fabricated by stereolithography process was investigated. A combination of scanning electron microscopy, micro-computed tomography scans and three-point bending tests were practiced systematically. The rheological behavior of ceramic paste was regulated distinctly by solid loading. As the solid loading increased, the degree of shrinkage decreased and the relative density increased for the sintered part. The sintered sample from 52 vol% ceramic paste presented the highest flexural strength with well densified microstructure. The research results promote property optimization of ceramic components fabricated by stereolithography method through material compositions and printability of ceramic paste, which simultaneously contributes to perfect support strategy for ceramic additive manufacturing.

Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

Effects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis

In this article, the combined effect of BOX thickness (TBOX) and ground-plane (GP) doping (NGP) on channel carrier mobility and analog figures of merit (FoMs) is investigated. It is reported that the thin BOX along with higher NGP will limit the electron/hole mobility of ultrathin body and BOX fully depleted silicon-on-insulator (UTBB FD-SOI) MOS transistors. The physics responsible for this observation is discussed in detail. The contrasting behavior of different GPs, the effect of TBOX scaling, and gate-length scaling on device behavior is also analyzed. It is also shown that in advanced UTBB FD-SOI MOS transistors, a tradeoff exists between transistor intrinsic gain, cutoff frequency, and non-linearity. In nMOS transistors, the best intrinsic gain and cut-off frequency can be achieved with ultrathin BOX and n-type GP (or with no GP), whereas the best linearity can be achieved with ultrathin BOX and p-type GP implant.

Gender Discrepancies in Perceptions of the Bodies of Female Fashion Models

For over 30 years, researchers and journalists have made the claim that men do not prefer the level of thinness typically embodied by female fashion models, along with the secondary claim that women overestimate the extent to which men find these ultra-thin bodies attractive. The current studies examined men’s and women’s perceptions of the bodies of fashion models shown in media images, as well as how each gender believed the other would perceive the models’ bodies. In Study 1, 548 U.S. college students rated the body size and attractiveness of 13 images of models from women’s fashion magazines. Respondents also indicated how they thought the other gender would rate the models on these dimensions. In Study 2, 707 men and women recruited from Amazon’s Mechanical Turk completed the same rating task. Overall, both men and women overestimated how ideal the other gender would find the models’ bodies (both in terms of thinness and attractiveness). This misperception was strongest when women estimated how men would react to the models’ bodies. Results were consistent with previous studies suggesting that men do not find the ultra-thin body ideal for women as attractive as women believe men do. These gender-based misconceptions may contribute to the negative effects of viewing ultra-thin media images on women’s body image.

Performance Evaluation and Device Physics Investigation of Negative-Capacitance MOSFETs Based on Ultrathin Body Silicon and Monolayer MoS2

The proposition of integrating the 2-D materials and ferroelectric negative-capacitance MOSFETs (NCFETs) was expected to have excellent steep slope ${I}$ – ${V}$ characteristics due to the combined advantages of both ultrathin body channel material and negative-capacitance effect. Recent experiments demonstrated the excellent steep slope features of 2-D material NCFETs. Therefore, it was important to understand the device physics of this characteristic, its performance projection, and the benchmark with NCFETs based on conventional Group IV materials. In this article, we conducted a computational study of 2-D material NCFETs based on MoS2 under the nonequilibrium Green’s function (NEGF)-Poisson self-consistent scheme with free-Gibbs energy calculation to judge the operating path in polarization–electric field (P–E) relation. Monolayer MoS2 (1L-MoS2) was chosen as channel material while various thickness of ultrathin body silicon (UTB-Si) for benchmark purpose. The results showed an excellent average subthreshold slope (SS) of ~25 mV/dec in 1L-MoS2 NCFETs compared to ~32 mV/dec of the UTB-Si counterparts. It was found that the steep-slope features in 1L-MoS2 NCFETs could be attributed to the more optimized capacitance matching in 1L-MoS2 NCFETs and tunneling currents at the subthreshold region.

Deep-Depletion Effect in SOI Substrates and its Application in Photodetectors With Tunable Responsivity and Detection Range

We present an interesting transient effect found in silicon-on-insulator (SOI) transistors, where the drain current responds slowly to a back-gate voltage ( ${V}_{\text {BG}}$ ) pulse. This transient mechanism is due to the deep-depletion region in the SOI substrate induced by the ${V}_{\text {BG}}$ pulse and has been validated by experimental and TCAD simulation results. The deep-depletion characteristic can be employed for photodetection in a fully depleted (FD)-SOI MOSFET device. We have measured the photoresponse of the FD-SOI MOSFET under various light illumination conditions and studied systematically the impact of the ${V}_{\text {BG}}$ pulse duty ratio, amplitude, and period on the responsivity and detection range. An optimized device structure, fabricated in an advanced ultrathin body and buried oxide (BOX) (UTBB) SOI technology, shows low operation voltage and extended detection range.