Ultra-thin Body Research Articles

TCAD-based investigation of 1/f noise in advanced 22 nm FDSOI MOSFETs

In this work, the mechanistic insights behind low-frequency noise (LFN) of the advanced ultrathin body and buried oxide fully depleted silicon-on-insulator based metal–oxide–semiconductor field effect transistor (MOSFET) are unveiled. The gate voltage-induced noise power spectral density (SVG) is inversely proportional to frequency f (i.e., SVG∝1/fγ, γ∼ 1 is the frequency exponent) for nMOSFET and pMOSFET. Detailed numerical simulations are performed and well calibrated to reported SVG vs f characteristics. Simulation results are consistent with the reported experimental observations. We demonstrate that LFN is caused by the charge carrier number fluctuation mechanism, which is originated by trapping and de-trapping of channel charge carriers via. bulk traps (from oxygen vacancies) in the hafnium dioxide (HfO2) layer, but not through traps at the silicon dioxide (SiO2)/channel interface. This work therefore explains the similar magnitude of SVG in both nMOSFET and pMOSFET observed experimentally and further suggests that oxygen vacancies inside gate oxides are critical to suppress the low-frequency noise in emerging high-k based MOSFETs.

2D-Penta-PdPS: Gate-Tunable and Thickness-Dependent Thermoelectric Transport.

Pentagonal two-dimensional (2D) materials are notable for unique properties derived from their Cairo pentagonal tiling topology. This study explores the thermoelectric potential of exfoliated penta-palladium-phosphorus-sulfur (PdPS) atomic layers, an air-stable 2D semiconductor with a puckered pentagonal low-symmetry structure, grown via chemical vapor transport (CVT). Thickness-dependent in-plane electrical conductivity (σ) and thermoelectric power factor (PF) of PdPS are investigated from 20-380 K, showing an increase in σ with thickness (11, 13, and 88-layer). Applying back-gate voltage (Vg) modulates the Fermi energy (EF), and as Vg decreases, the Seebeck coefficient (S) rises, achieving S of -700µVK-1 for 11-layer PdPS at -10V, significantly higher than the -400 µVK-1 for 88-layer PdPS. The PF increased with decreasing thickness, peaking at ≈50µW m-1K-2 for 11-layer PdPS, about twice than that of 88-layer PdPS. The high electron mobility (µe) in PdPS is confined to a narrow temperature range, peaking at 300 cm2Vs-1 at 100 K, marking the transition temperature from ionized impurity scattering to acoustic phonon scattering mechanism, consistent across all layer counts. This work highlights the significant impact of quantum confinement in ultrathin bodies in enhancing thermoelectric performance across a wide temperature range.

Carrier Mobility Enhancement in Ultrathin-Body InGaAs-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Based on Dual-Gate Modulation

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al2O3 interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 1013 cm−2 was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field.

A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Abstract IIn this paper, two substrate optimization approaches of triple stacked Nanosheet FET (SNSHFET), namely optimization of buried oxide and selective deposition of punch through stopper (PTS) substrate, have been examined and simulations have been carried out using Technology Computer-Aided (TCAD) software. A comprehensive study of leakage current and key electrical characteristics (I¬ON, VT, SS, DIBL) have also been extracted based on variation in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. GIDL current also increases with increased doping of the source and drain. Also, the impact of ultra-thin body substrate in SNSHFET is studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in Inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed at the channel-drain and gate-substrate overlap region for understanding the physical insights of leakage current in the SNSHFET. This work also answers the dependency of GIDL current on the gate and drain voltage supply respectively. In addition to that, how GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. The 3 nm-based SNSHFET is designed and its electrical and GIDL characteristics are compared with novel devices like Forksheet FET and Complementary FET.

Analysis of 10 nm Strained Channel Double Gate Ultra-Thin Body Junctionless MOSFET

Numerous technological improvements and innovative device architecture have been thoroughly explored and tested for continually downscaling components without compromising on performance metrics. The most simplified structure that has been introduced so far is the junctionless transistors. Junctionless transistors have been shown to exhibit excellent electrical behavior with improved short-channel effects. The major challenges with junctionless based transistors are low ON-current drive and high device variability. Strain engineering has been proven to be a viable option to enhance the ON-current performance of the MOSFET. This work incorporated strained silicon in double gate junctionless ultra-thin body MOSFET (DG-JL UTB MOSFET), which enhanced the mobility of the charge carrier as a result of which ON current behavior improves. The simulated results show 30.2% enhancement in the ON-current, subthreshold current reduced to nearly half, ION/IOFF ratio is increased by three times, and Drain-induced barrier lowering (DIBL) reduced by 25.1% with respect to unstrained device. Analog performance metrics are also calculated for the considered device design. With strained silicon, the value of Gm is increased by more than 30% and transconductance generation factor (TGF) is increased by 28.27% in reference with the unstrained device.

Breakdown Voltage Enhancement of Nanosheet Transistors by Ultrathin Bodies

Breakdown Voltage Enhancement of Nanosheet Transistors by Ultrathin Bodies

Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2.

Van der Waals Contact for Two-Dimensional Transition Metal Dichalcogenides.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

The trap-induced noise characteristics of fully-depleted SOI (FDSOI) MOSFETs with ultra-thin body and buried oxide are essential for high-performance applications. However, accurate noise modeling and traps identification of the device remains challenging. In this work, we investigate the noise characteristics of FDSOI MOSFETs arising from traps in both the gate dielectric (GD) and the buried oxide (BOX). By using TCAD tool, we examine the noise generated by traps at various energy levels and spatial positions in GD and BOX under different biases. The simulation results reveal that traps in GD and BOX exhibit distinctly different behaviors as Vg increases, providing insights for identifying traps from noise measurement results.

Analysis and 3D TCAD simulations of single-qubit control in an industrially-compatible FD-SOI device

In this study, 3D simulations are introduced to analyze electric-dipole spin resonance (EDSR) for a spin qubit defined in a 28nm-node Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted Silicon-On-Insulator (FD-SOI) device operated at cryogenic temperatures. The device under consideration is designed to be compatible with STMicroelectronics’ standard fabrication techniques. The simulations predict the experimental and device parameters (e.g. drive amplitude, leakage, and Rabi frequency) required to make EDSR a viable means of qubit control before the device is fabricated. This work highlights how 3D TCAD tools which can simulate quantum-mechanical effects can help steer the design of quantum devices.

Lateral junctions of transition metal dichalcogenides as ballistic channels for straintronic applications

In the context of advanced nanoelectronics, two-dimensional semiconductors such as transition metal dichalcogenides (TMDs) are gaining considerable interest due to their ultimate thinness, clean surface and high carrier mobility. The engineering prospects offered by those materials are further enlarged by the recent realization of atomically sharp TMD-based lateral junctions, whose electronic properties are governed by strain effects arising from the constituents lattice mismatch. Although most theoretical studies considered only misfit strain, first-principles simulations are employed here to investigate the transport properties under external deformation of a three-terminal device constructed from a MoS2/WSe2/MoS2 junction. Large modulation of the current is reported owing to the change in band offset, illustrating the importance of strain on the p–n junction characteristics. The device operation is demonstrated for both local and global deformations, even for ultra-short channels, suggesting potential applications for ultra-thin body straintronics.

TID response of hybrid FinFET with modified gate dielectric

The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose.

Ultrathin Body and Buried Oxide SOI MOSFETs With Non-LDD Source/Drain Extensions: A Simulation Study

Ultrathin Body and Buried Oxide SOI MOSFETs With Non-LDD Source/Drain Extensions: A Simulation Study

(Invited) Stacking High Mobility Channels

Beyond 3 nm node, the transistor architecture of stacked channel gate-all-around (GAA) FETs can replace FinFETs for advanced technology node due to the improvement of power, performance, and area by the enhanced short channel control, design flexibility, and drive current per footprint. High ION and small parasitic RC are the keys to extend nanosheet technologies for N+1 and N+2 nodes. To extend nanosheets to next nodes, we have demonstrated additional enabling knobs such as high mobility channels, high-k gate dielectrics, and highly stacked channels to effectively increase the ION for high performance. Beyond stacked nanosheets, new transistor architectures such as TreeFET (a combination of FinFET and stacked nanosheets) and CFET (3D stacked n and p FETs) can further enable cell height scaling. CFETs and atomic channels have potentials to be used in A5 and A2 nodes according to the transistor roadmap by IMEC [1], respectively. Note that ultrathin body as thin as 1 nm can be considered as atomic channels for nearly ideal SS and high ION/IOFF for low power application.First of all, high mobility channel material is the key factor to improve performance CV/I. As a result, Ge/GeSi and GeSn are the target high mobility channels for nFETs and pFETs, respectively. For nFETs, Ge is an attractive option for high mobility channel to boost the ION thanks to its higher electron mobility than Si [2]. For pFETs, strained GeSn has higher hole mobility than Ge to improve the ION for pFETs due to the hole effective mass reduction under compressive strain [3]. For a fixed footprint, the vertically highly stacked GAA channels can provide large ION to achieve high performance and area scaling for advanced technology node.In addition to high mobility channel, the performance of GAAFET can be improved by scaling down gate oxide thickness. However, the gate leakage problem increases with scaling down the gate oxide thickness. As a result, high-k materials were proposed as gate oxide for gate leakage reduction and performance enhancement in GAAFETs. Plasma-enhanced atomic layer deposition (PEALD) HfxZryO2 was reported to achieve high-k value by optimizing the Hf and Zr content [4], respectively. In this work, a high k value of 47 is achieved in Hf0.2Zr0.8O2 alloy. Furthermore, the high-k gate dielectrics is integrated into stacked GAAFETs successfully.However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [5-7]. Ultrathin body device can effectively reduce the IOFF, but the mobility degradation is observed as the channel thickness decreases below 5nm due to surface roughness scattering. Moreover, the high mobility GeSn can afford some mobility loss due to the ultrathin body [8]. Furthermore, the ION can be further improved by channel stacking with the suppression of IOFF by the ultrathin body.For Si nanosheets, the mismatch between hole mobility and electron mobility in nanosheets [9] might lead to potential design challenges of CMOS. As a result, the TreeFET transistor architecture combining with FinFETs and stacked nanosheets is proposed [10] and experimentally demonstrated [11] as a candidate beyond nanosheets. TreeFETs with {100} surfaces can enhance the electron mobility of Si, while {110} sidewalls are beneficial to hole mobility for both Si and Ge. TreeFETs with additional fin interbridges (IB) between nanosheets can increase Weff and enhance ION per footprint for high-performance devices beyond FinFETs and stacked nanosheets.3D transistor stacking can enable further cell height scaling and extend Moore's law scaling. The pFET and nFET are able to fold on each other to reduce 50% of inverter cell area ideally in CFET [12, 13], as a promising transistor architecture beyond stacked nanosheets. As compared to the sequential 3D process, no wafer bonding or layer transfer is required in the monolithic 3D process. Moreover, monolithic 3D by epitaxy can reduce the FEOL cost and the parasitic RC as compared to sequential 3D. The high mobility channel material of GeSi is used for CFET demonstration in this work [14]. Heavily doped sacrificial layers are beneficial for S/D resistance reduction by thermal annealing during the device fabrication. Reportedly, dielectric layers in S/D regions are used for the electrical isolation between n/p FETs in CFET structure [15], but the complicated S/D recess and dual S/D selective epi regrowth are required. In this work, a simple process without S/D selective epi regrowth can achieve self-aligned CFETs with multiple P/N junction isolation to effectively reduce the leakage current. Acknowledgements- This work is supported by National Science and Technology Council (111-2218-E-002-040-MBK, 111-2634-F-A49-008-, and 111-2622-8-002-001-), Ministry of Education (NTU-CC-112L890901), and Taiwan Semiconductor Research Institute (TSRI), Taiwan. Figure 1

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Total ionizing dose and single event effect response of 22 nm ultra-thin body and buried oxide fully depleted silicon-on-insulator technology

The test chip including transistors and Static Random Access Memory (SRAM) is proposed and fabricated by an advanced 22 nm Ultra-Thin Body and Buried Oxide Fully Depleted Silicon-on-Insulator (UTBB FD-SOI) technology. Experimental results of Co-60 irradiation and heavy ion experiments are presented. Total Ionizing Dose (TID) experiment results show that the threshold voltage shift of the transistor is about 100 mV when the dose is 500 krad(Si) and the SRAM irradiated to a dose of at least 300 krad(Si) can maintain its functionality, which means that 22 nm UTBB FD-SOI devices exhibit significantly improved total dose tolerance performance compared to the previous generation process. TID-induced threshold voltage shift in conventional-well nMOSFET can be mitigated by applying biasing to back-gate, while back-gate biasing is invalid for TID mitigation of the conventional-well pMOSFET. Heavy ion experimental results make known that 22 nm UTBB FD-SOI technology has contributions to Single Event Effect (SEE) hardness and the hardened SRAM has higher single event upset (SEU) tolerance and even SEU immunity. The research indicates that the circuits manufactured by 22 nm UTBB FD-SOI technology have great potential space applications in harsh radiation environments.

Doping-less MultiGate Inverted-T shape FET device with Schottky source/drain contacts

A dopingless multi-gate inverted-T Shape device has been proposed with Schottky source/drain contacts. Gate oxide engineering is performed on the proposed device, and its two configurations namely Hetero-Dielectric (HD) and Gate-Stack (GS) are implemented. The proposed HD configuration of dopingless inverted-T shape FET has asymmetric oxide; where oxide (HfxTi1-xO2) having high value of dielectric is placed on source side and SiO2 with lower dielectric value is placed on drain side. The designed device showcase a leakage current of approximately 10−16 A in contrast to the traditional junctionless FET which has leakage of 10−10 A. Also, comparative analysis of the GS and HD dopingless multi-gate inverted-T shape transistor is outlined at different parameters including channel length, fin width and Ultra-thin body thickness. AC analysis of the device has been done to evaluate cut-off frequency and gain bandwidth product. Additionally, p-channel configuration is formulated in conjunction with n-channel MOS configuration to investigate the device's suitability for applications employing CMOS technology.

Simulation process flow for the implementation of industry-standard FD-SOI quantum dot devices

The spin of an electron confined to a semiconductor quantum dot is one of the main technology platforms currently evaluated in the pursuit of qubit implementation. In this study, we developed and optimized a full simulation process flow used to model an Ultra-Thin Body and Buried oxide (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) quantum dot device fabricated using STMicroelectronics' standard manufacturing process. Here, we report optical, geometrical, electrical, and quantum numerical results that allowed us to assess the device performance before its eventual fabrication.

2D Dual Gate Field-Effect Transistor Enabled Versatile Functions.

Advanced computing technologies such as distributed computing and the Internet of Things require highly integrated and multifunctional electronic devices. Beyond the Si technology, 2D-materials-based dual-gate transistors are expected to meet these demands due to the ultra-thin body and the dangling-bond-free surface. In this work, a molybdenum disulfide (MoS2 ) asymmetric-dual-gate field-effect transistor (ADGFET) with an In2 Se3 top gate and a global bottom gate is designed. The independently controlled double gates enable the device to achieve an on/off ratio of 106 with a lowsubthreshold swing of 94.3 mV dec-1 while presenting a logic function. The coupling effect between the double gates allows the top gate to work as a charge-trapping layer, realizing nonvolatile memory (105 on/off ratio with retention time over 104 s) and six-level memory states. Additionally, ADGFET displays a tunable photodetection with the responsivity reaching the highest value of 857 A W-1 , benefiting from the interface coupling between the double gates. Meanwhile, the photo-memory property of ADGFET is also verified by using the varying exposure dosages-dependent illumination. The multifunctional applications demonstrate that the ADGFET provides an alternative way to integrate logic, memory, and sensing into one device architecture.