Ultra Low-k Dielectric Materials Research Articles

Investigation of Fluoro-Carbon Layer on Dense Sicoh Formed during CF4 and CF4/C4F6 Based Continuous Wave Plasma Etch

Motivation: Plasma etching of low-k and ultra low-k (ULK) dielectric materials have seen a tremendous growth in deep nanoscale applications. Fluorocarbon based gases are the forerunners in etching low-k dielectrics as they are the F suppliers necessary to remove Si and C from SiCOH material. Different FC gases in combination with the additive gases contribute differently to the etch behavior of SiCOH due to differing reaction chemistry and formation of Fluorocarbon layer as an interfacial layer between plasma front and dielectric front [i]. Due to dynamic formation and etching of FC Layer happening at the dielectric surface, understanding FC layer properties in each gas plasma is the starting step to control etch rate and plasma induced damage in Low-k dielectrics. This paper aims to study and compare FC layer deposition by different gases grouped into CF4 and CF4/C4F6 family with N2, O2 and H2 as additive gases in each group. FC layer thickness, etch rate, optical properties of etched SiCOH and chemical composition of the FC layer by different plasma treatments have been presented in this work. Methodology: Dense SiCOH (k=2.75 and Open Porosity: 7%) with initial thickness of 157±3nm is deposited on 300mm Si Wafer with a thin SiO2 adhesion layer in between. These wafers are blanket etched in a commercial etch chamber with the given gas combinations (CF4, CF4/N2, CF4/O2, CF4/H2; CF4/C4F6, CF4/C4F6/N2, CF4/C4F6/O2, CF4/C4F6/H2) for same amount of time, total gas flow rate, similar power, pressure and temperature settings.Post Etch blanket wafers are subjected to various in-line and off-line metrology tools. In-line spectroscopic ellipsometer is used to model complex refractive index and thickness of individual layers. Tauc-Lorentz model best describes the FC layer whereas Cauchy model describes the dielectric [ii]. In-line XPS was carried out to probe the surface of FC layer and gain chemical information. Furthermore depth profile of etched layer is carried out by sputtering the surface with low power Ar ions to study variations in chemical composition with the layer depth. SEM is used to see the cross section profile and verify the results from above method Observation: Thickness evaluation from the dispersion models shows that the CF4 group has higher etch rate and lower FC layer thickness compared to CF4/C4F6 group. C4F6 has higher polymerization ability by the virtue of its lower F/C ratio. Amongst each group, Oxygen as additive gas shows the highest etch rate and least FC thickness followed by Nitrogen whereas Hydrogen has least etch rate but highest FC layer thickness. Under given etch conditions with CF4/C4F6/H2 plasma, deposition rate was higher than etching rate leading to stack growth (Fig.1a). Hydrogen supports polymerization by scavenging Fluorine away and aids in thicker FC films.XPS chemical composition shows Fluorine diffusion through FC layer into the dielectric layer bringing changes to its pristine structure. This affects Carbon% across the etched dielectric thickness (Fig.1b). Thicker the FC layer is, closer is the Carbon % to pristine SiCOH. Presence of surficial Nitrogen in the nitrogen containing plasmas shows nitrogen reacts with SiCOH Carbon, forms CN compounds and increases the etch rate. FC layer shows presence of CF3 radicals on the surface and decrease fast with the depth, followed by CF2 radicals. CF radicals are in larger quantity and are present deepest into the FC Layer. Presence of polymerized C-C and C-CFx bonds increases with the FC Layer depth and offset with increase of C-Si bond near the SiCOH interface. Conclusion: This paper shows comparison of Etch Rate and FC layer thickness during SiCOH etch using different gas combinations in the CCP plasma chamber. Thickness correlation between ellipsometric model data and XPS depth profile followed by SEM cross section measurement of layer thickness point towards the correctness of dispersion models for each layer. These models can be used for quick inline post etch metrology useful for process control. O2 containing plasmas are too aggressive on the dielectric with negligible FC layer formation, while H2 containing plasmas are less damaging but exhibit very small etch rate. CF4/C4F6/N2 plasma is the optimum combination for Low-k dielectric etch amongst other combinations in terms of desired etch rate and lower reduction in Carbon %. Relative concentration and penetration depth of different CFx radicals in FC film suggests its influence on film structure.

Plasma Induced Damage Reduction of Ultra Low-k Dielectric by Using Source Pulsed Plasma Etching for Next BEOL Interconnect Manufacturing

In order to reduce the interconnect resistance and capacitance (RC) time delay of a semiconductor integrated circuit, a more porous dielectric material is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etching system. RF pulsed plasmas generated more polymerizing species and less UV compared to continuous wave plasmas and showed reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric patterned with a TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages, which was estimated by the thickness loss of sidewall low-k material after dipping into a diluted HF solution. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC time delay related to plasma damage for the next interconnect manufacturing technology.

Etch Damage Reduction of Ultra Low-k Dielectric by Using Pulsed Plasmas

To reduce interconnect resistance and capacitance (RC) time delay of semiconductor integrated circuit, the dielectric material with more porosity is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric using C4F8-based gases, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etch system. RF pulsed plasmas generated higher carbon-rich radicals in the plasma and less charging effect on the dielectric material surface compared to continuous wave plasmas and, therefore, showed a reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric with a patterned TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC delay related with plasma damage for the next interconnect technology.

Leakage current induced by surfactant residues in self-assembly based ultralow-k dielectric materials

In this work, we studied low-field leakage currents in the self-assembly based spin-on low-k dielectrics (k = 2.2) as it may be affected by the degree of the organic template decomposition. The distinct role of the template residues could be examined due to the remarkably different rate of organosilica matrix cross-linking and template decomposition during the hard-bake process. We found that the incomplete decomposition of the sacrificial organic phase is responsible for increased low-field leakage current through the dielectric. The analysis of photocurrent spectra and the results of electron resonance spectroscopy suggest that the degradation of electrical performance can be attributed to the presence of defect states ∼5 eV below the insulator conduction band induced by the residues in the form of oxidized sp3-carbon chains. The lowest leakage current is attained in the template-free material obtained by introduction of additional broadband UV-assisted curing (λ > 200 nm).

Enhancement of seeding for electroless Cu plating of metallic barrier layers by using alkyl self-assembled monolayers

Tethering a self-assembled monolayer (SAM) on ultralow-k (porous) dielectric materials as a seed-trapping layer for electroless Cu plating has been extensively studied. By contrast, literature on direct electroless Cu plating of metallic barrier layers assisted by SAMs is scarce. Therefore, Ta, a crucial component of barrier materials for Cu interconnect metallization, was investigated as a model substrate for a new seeding (Ni catalyst formation) process of electroless Cu plating. Transmission and scanning electron microscopies indicated that catalytic particles formed on Ta films through TaOH groups tend to become aggregates with an average size of 14nm and density of 2×1015m−2. By contrast, Ta films with a plasma-functionalized SAM tightly bound catalytic particles without agglomeration, thus yielding a markedly smaller size (3nm) and higher density (3×1016m−2; one order greater than those formed by other novel methods). X-ray photoelectron spectroscopy clearly identified the types of material species and functional groups induced at each step of the seeding process. Moreover, the phase of the catalytic particles, either nickel alkoxide, Ni(OH)2, or metallic Ni, along with the seed-bonding mechanism, was also unambiguously distinguished. The enhancement of film-formation quality of Cu by the new seeding process was thus demonstrated.

Application of STEM EELS Quantification Relative Compositional Ratio Mapping to Characterize SiCOH - Ultra Low-k Dielectric Materials in Si-based Devices

Application of STEM EELS Quantification Relative Compositional Ratio Mapping to Characterize SiCOH - Ultra Low-k Dielectric Materials in Si-based Devices

Minimize Electron Beam Damage during Characterization of Carbon-Depletion in Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Minimize Electron Beam Damage during Characterization of Carbon-Depletion in Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Characterization of Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Characterization of Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Dielectric Properties of Selected Metal–Organic Frameworks

The electronic structure of a class of [Zn4O(CO2)6] based metal–organic frameworks (MOFs) is theoretically analyzed by means of density functional perturbation theory. The calculated static dielectric constants vary in a range between 1.33 and 1.54, characterizing the structures as ultralow-k dielectric materials and confirming earlier estimates qualitatively. We also present the results of first-principle calculations of the real and imaginary parts of the dielectric function and give the frequency-dependent dielectric constant up to the near-ultraviolet, which is important for high frequency semiconductor and optical applications of MOFs. The dielectric and electronic properties are governed by the linker molecules, so that the band gap and the dielectric constant can be engineered.

(Invited) Barrier Slurry Innovation for Cu-ULK Process

With the application of Ultra low-k dielectric material in the advanced nodes, more and more challenges are elevated on barrier CMP. High removal rates of TEOS and barrier films are required to enable an effective removal, while tunable Cu RR and low ULK RR are needed to control the topography and stop in ULK layer. The k value shift of polished ULK also should be minimized. In this paper, we will report a barrier slurry for this application including slurry additives effect on removal rate selectivity, topography and k value. The corrosion control capability is also evaluated by soaking test. Through slurry formulation tuning, an optimal topography with good within wafer and within die non-uniformity are obtained. The control capability in removal rate and selectivity, k value shift of polished ULK, topography, and Cu corrosion were demonstrated.

Design of lamellar structured POSS/BPZ polybenzoxazine nanocomposites as a novel class of ultra low-k dielectric materials

A novel class of lamellar structured polyhedral oligomeric silsesquioxane/bisphenol Z (POSS/BPZ) polybenzoxazine (PBz) nanocomposites was successfully designed by a facile one-step copolymerization technique.

Influence of porosity on dielectric breakdown of ultralow-k dielectrics

The effect of porosity on the electrical properties of porogen-free ultralow-k dielectric materials was demonstrated using a special curing process that allows a separate control of porosity and matrix properties. It is shown that the leakage current was insensitive to porosity, suggesting a bulk conduction mechanism. On the other hand, higher porosity leads to lower breakdown voltage, indicating that porosity can degrade the electrical reliability performance of the dielectric material. The observed lower breakdown field is explained in terms of the amount of cage structure in the film, the exacerbation of strain in the Si–O–Si backbone structure by an external electric field, and local field enhancements near the pores, thereby making the Si–O bond highly susceptible to breakage.

Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement

To improve resistance-capacitance delay, porous ultra low-k dielectric materials are used in advanced copper damascene integration. However, the BEOL processes often lead to low-k film damage by removing the hydrophobic groups Si-CH3, and convert partially low-k materials surface from hydrophobic to hydrophilic one. During the wet related processes, the hydrophilic porous low-k film surface is easy to absorb moisture and potentially increase k-value. In this work, we developed the processes that can maintain ultra low-k film k-value either by repairing low-k damage or by removing moistrue. Dry etch plasma process is one of the main steps to result in low-k film damage. Post etch treatment (PET) was optimized to repair porous low-k film surface due to the etch damage. This improved process with less low-k damage can significantly reduced the moisture absorption in the following wet process and improve the capacitance by about 10%. Various thermal treatments post wet and post CMP processes were studied, including temperature, gases and pressures. From our results, post wet clean heat treatment can improve capacitance by about 5% and post CMP heat treatment can improve capacitance by about 10%. To decrease moisture absorption from atmosphere after the wafers were processed thru CMP, queue time from CMP to NDC deposition also was studied and the safe specification was also defined.

Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

Lead-Free Flip-Chip Packaging Affects on Ultralow-$k$ Chip Delamination

Ultralow-k dielectric materials generally show weak mechanical strength (E <; 8 GPa), a high coefficient of thermal expansion (5 ppm/°C-8 ppm/°C), and poor adhesion ( <; 5 J/m2-10 J/m2). As a result, ultralow-k delamination becomes a major failure mode after the packaging reliability test. This paper investigates the propagation mechanism of ultralow-k delamination during the temperature cycling test (TCT). A full understanding this delamination processes is critical for selecting an adequate underfill and protecting both the ultralow-k chip and the lead-free solder bump. This paper shows that the ultralow-k delamination of lead free-flip-chip packaging after TCT starts near the outermost bump, and then propagates simultaneously to the corner and the central area of the chip. Finite element simulation is employed to analyze the packaging stress distribution and the ultralow-k delamination mechanism. An underfill selection methodology is proposed to prevent ultralow-k delamination and lead-free solder bump cracks. In addition, an underfill experiment is carried out to confirm the finite element simulation result and verify the ultralow-k delamination mechanism.

New generation of reactive pre-clean prior to barrier–seed deposition to preserve ULK integrity

Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical properties due to porosity increase. Consequently, ULK dielectrics are more prone to be damaged during plasma treatment in interconnects build [1]. Pre-clean processes prior to barrier/seed deposition are a potential area of concern for ULK integrity. Reactive pre-clean processes based on He/H2 plasma are investigated in this paper through two types of hardware. The new pre-clean chamber is an upgrade of conventional pre-clean hardware and combines optimized H2 plasma and active wafer temperature control to ensure efficient copper oxide reduction [3] and via cleaning. The aim of the paper is to evaluate performance of the new generation of reactive pre-clean compared to conventional hardware. To overcome ULK dielectric integration challenge, pre-clean processes need to ensure efficient copper oxide reduction and via bottom cleaning with minimum impact on ULK material properties. The ''new reactive pre-clean'' addresses these requirements for k=2.5 ULK materials. The new reactive pre-clean demonstrates a robust process window over a wide range of temperature and pressure settings for all characterized aspects. The ''new reactive pre-clean'' technology is seen to be a promising pre-clean candidate for next generation of porous ULK dielectric material ([email protected]?2.5) integration for 28nm node and beyond.

Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond

Metrology and approaches necessary for selection of ultra low-k dielectric materials for future generation of IC devices are discussed. It is shown that porogen residue (sp2 hybridized carbon) formed during the UV curing of porogen based PECVD low-k materials increases the leakage current density and decreases the breakdown field. The amount of porogen residue increases with porosity because of larger amount of co-deposited porogen. Electrical characteristics of these films are significantly worse in comparison with low-k films prepared by using of self-assembling approaches without porogen. Therefore, utilization of porogen based technologies for preparation of ultra low-k films is limited. New metrologies allowing evaluation of intrinsic properties of low-k materials are discussed. It is shown that UV spectroscopy and a unique planar capacitor test vehicle are extremely important for evaluation of intrinsic properties of ultra low-k films.

Metal-organic frameworks as promising candidates for future ultralow-k dielectrics

A class of Zn4O(CO2)6-based metal-organic frameworks (MOFs) is theoretically analyzed with respect to suitability as an interlayer dielectric material for applications in semiconducting devices. The static dielectric constant is calculated using the Clausius–Mossotti approach. For 3 of about 30 of the considered MOFs excellent combinations of ultralow dielectric constant, elastic bulk modulus, and gap energy are found favoring these materials as outstanding candidates for future ultralow-k dielectric materials.

Interactions of Metal-Organic PEALD TaN with Ultra-Low k Dielectric Materials

Both dense and porous patterned ultra-low k (ULK) substrates have been characterized in terms of their interaction with TaN grown by plasma enhanced atomic layer deposition (PEALD). The conformal nature of the deposited TaN films by PEALD was demonstrated on a patterned dense oxide substrate. For the case of ULK dielectric materials with a dielectric constant of 2.55 (ULK2.55), penetration of TaN into the ULK matrix was observed for porous ULK2.55 while dense ULK2.55 did not exhibit any significant penetration of TaN. Both hydrogen plasma-based PEALD TaN and ammonia plasma-based PEALD TaN processes were shown to display a similar interaction with ULK2.2. A dielectric pore-sealing layer applied on patterned ULK2.2, prior to the deposition of TaN, enabled a significant reduction in PEALD TaN penetration as observed at ULK sidewalls.

Designing Ultra Low-k Dielectric Materials for Ease of Patterning

AbstractOrganosilicate materials with dielectric constants (k) ranging from 3.0 to 2.2 are in production or under development for use as interlayer dielectric materials in advanced interconnect logic technology. The dielectric constant of these materials is lowered through the addition of porosity which lowers the film density, making the patterning of these materials difficult. The etching kinetics and surface roughening of a series of low-k dielectric materials with varying porosity and composition were investigated as a function of ion beam angle in a 7% C4F8/Ar chemistry in an inductively-coupled plasma reactor. A similar set of low-k samples were patterned in a single damascene scheme. With a basic understanding of the etching process, we will show that it is possible to proactively design a low-k material that is optimized for a given patterning. A case study will be used to illustrate this point.