Ultra-low Area Research Articles

A quantum-based ultra-low area nano-architecture for morphological processes

A new transistor-less field-coupled nanocomputing (FCN) method for ultra-scale “nanochip” integration is called quantum-dot cellular automata (QCA). Electrostatic repulsion between electrons and the electron tunneling process in quantum dots is employed in QCA to depict digital circuitry. QCA technology is able to achieve higher clock speed, lower occupied chip area, and more energy efficiency than traditional complementary metal-oxide semiconductor (CMOS) technology. Irreversible majority gates are commonly utilized as the main building blocks in the development of QCA circuits. In order to create highly energy-efficient QCA circuits, some research has recently presented digital image processing design strategies that use majority gates as the primary building block. Image processing, which encompasses picture analysis, enhancement, and correction, is used to extract information from images and improve their quality. Among the primary methods for processing images are picture enhancement, restoration, compression, object recognition, and machine vision applications. However, morphological procedures such as dilation and erosion constitute the fundamental component of image processing and are widely applied in practical applications. In this study, QCA-optimized nanostructures are presented for applications in mathematical morphology, serving as erosion and dilation operators. The completed circuit comprises 33 cells and exhibits a temporal delay of approximately 0.75 during each clock cycle. A comparison with the best equivalent nano-architecture demonstrates a significant improvement in cell performance, scalability, and latency.

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

Spiking neural networks (SNNs) promise to perform tasks currently performed by classical artificial neural networks (ANNs) faster, in smaller footprints, and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls for finely-tuned custom implementations to keep pushing towards more efficient systems. To that end, we examined the architectural design space for executing spiking neuron models on FPGA platforms, focusing on achieving ultra-low area and power consumption. This work presents an efficient clock-driven spiking neuron architecture used for the implementation of both fully-connected cores and 2D convolutional cores, which rely on deep pipelines for synaptic processing and distributed memory for weight and neuron states. With them, we developed an accelerator for an SNN version of the LeNet-5 network trained on the MNIST dataset. At around 5.5 slices/neuron and only 348 mW, it is able to use 33% less area and four times less power per neuron as current state-of-the-art implementations while keeping low simulation step times.

A sub-10 μm Ion Conducting Membrane with an Ultralow Area Resistance for a High-Power Density Vanadium Flow Battery

A sub-10 μm Ion Conducting Membrane with an Ultralow Area Resistance for a High-Power Density Vanadium Flow Battery

Intravital microscopic observation of the microvasculature during hemodialysis in healthy rats

Hemodialysis (HD) provides life-saving treatment for kidney failure. Patient mortality is extremely high, with cardiovascular disease (CVD) being the leading cause of death. This results from both a high underlying burden of cardiovascular disease, as well as additional physiological stress from the HD procedure itself. Clinical observations indicate that HD is associated with microvascular dysfunction (MD), underlining the need for a fundamental pathophysiological assessment of the microcirculatory consequences of HD. We therefore successfully developed an experimental small animal model, that allows for a simultaneous real-time assessment of the microvasculature. Using in-house built ultra-low surface area dialyzers and miniaturized extracorporeal circuit, we successfully dialyzed male Wistar Kyoto rats and combined this with a simultaneous intravital microscopic observation of the EDL microvasculature. Our results show that even in healthy animals, a euvolemic HD procedure can induce a significant systemic hemodynamic disturbance and induce disruption of microvascular perfusion (as evidence by a reduction in the proportion of the observed microcirculation receiving blood flow). This study, using a new small animal hemodialysis model, has allowed direct demonstration that microvascular blood flow in tissue in skeletal muscle is acutely reduced during HD, potentially in concert with other microvascular beds. It shows that preclinical small animal models can be used to further investigate HD-induced ischemic organ injury and allow rapid throughput of putative interventions directed at reducing HD-induced multi-organ ischemic injury.

Robust wrinkled MoS2/N-C bifunctional electrocatalysts interfaced with single Fe atoms for wearable zinc-air batteries

The ability to create highly efficient and stable bifunctional electrocatalysts, capable of oxygen reduction reaction (ORR) and oxygen evolution reaction (OER) in the same electrolyte, represents an important endeavor toward high-performance zinc-air batteries (ZABs). Herein, we report a facile strategy for crafting wrinkled MoS2/N-doped carbon core/shell nanospheres interfaced with single Fe atoms (denoted MoS2@Fe-N-C) as superior ORR/OER bifunctional electrocatalysts for robust wearable ZABs with a high capacity and outstanding cycling stability. Specifically, the highly crumpled MoS2 nanosphere core is wrapped with a layer of single-Fe-atom-impregnated, N-doped carbon shell (i.e., Fe-N-C shell with well-dispersed FeN4 sites). Intriguingly, MoS2@Fe-N-C nanospheres manifest an ORR half-wave potential of 0.84 V and an OER overpotential of 360 mV at 10 mA⋅cm-2 More importantly, density functional theory calculations reveal the lowered energy barriers for both ORR and OER, accounting for marked enhanced catalytic performance of MoS2@Fe-N-C nanospheres. Remarkably, wearable ZABs assembled by capitalizing on MoS2@Fe-N-C nanospheres as an air electrode with an ultralow area loading (i.e., 0.25 mg⋅cm-2) display excellent stability against deformation, high special capacity (i.e., 442 mAh⋅g-1Zn), excellent power density (i.e., 78 mW⋅cm-2) and attractive cycling stability (e.g., 50 cycles at current density of 5 mA⋅cm-2). This study provides a platform to rationally design single-atom-interfaced core/shell bifunctional electrocatalysts for efficient metal-air batteries.

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -247dB, and normalized TR and area (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub> ) of -262dB.

Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods

Realization of an ultra low power and area efficient SC SAR ADC architecture using single and two step reset methods

SSTRNG: self starved feedback SRAM based true random number generator using quantum cellular automata

The information are need to modulate using irreproducible and unpredictable digital bit stream to get a secure digital communication systems. Hence, True random number generator (TRNG) is a significant aspirant in digital circuit to yield unpredictable digital bit stream. In this assignment self starved feedback SRAM based TRNG is proposed in quantum cellular automata (QCA) technology. Moreover, QCA technology is adopted to design TRNG components due to its features like ultra low power dissipation, low area and ultra high operating frequency. The proposed TRNG is comprised of self starved feedback circuit and floating clock generator. Again, the basis of self starved feedback circuit is a single bit QCA SRAM cell, which extracts the random digital bit. Furthermore, to enhance the randomness, floating clock generator is implemented across self starved feedback circuits input. The functionality of proposed TRNG is accomplished through QCA Designer tool and its architecture is also passed NIST statistical test of randomness. Hence proposed 8 bit TRNG can be interpreted as a novel contender for security applications due to its 14.82 GHz operating frequency, 0.36 μm2 area, latency of 1 QCA clock cycle, 28.53 meV average power dissipation and high tail probability of NIST test battery report in QCA technology.

A TDC-less all-digital phase locked loop for medical implant applications

A TDC-less, ultra-low area and low power all-digital phase locked loop (ADPLL) has been designed for use in biomedical implant transceivers. The proposed ADPLL eliminates the use of LC oscillator and time-to-digital converter (TDC) for achieving a low power and low area implementation suitable for biomedical implants. Circuit design techniques such as capacitive boosting and fractional capacitor tuning have been applied to the ring oscillator of the proposed ADPLL for achieving good jitter performance. The ADPLL has been fabricated in 40 nm CMOS and occupies an active area of only 0.0186 mm2. Measurement results demonstrates that the ADPLL can provide differential output signal with a frequency range from 330 MHz to 470 MHz while operating at a supply of 0.68 V. The ADPLL consumes a power of 248.62 µW at 0.68 V supply while running at an output frequency of 401 MHz and exhibits an rms jitter of 11.88 ps. The measured phase noise of the ADPLL is −98.76 dBc/Hz at 1-MHz frequency offset. The ADPLL's applicability in cochlear implant applications is also discussed.

Flame Spread Over Ultra-thin Solids: Effect of Area Density and Concurrent-Opposed Spread Reversal Phenomenon

There are no existing experimental studies of flame spread rate trends for ultra-thin solid samples. Previous theory has predicted that for concurrent flame in kinetic regime, the flame spread rate decreases as the sample thickness decreases and there is a critical thickness below which burning is not possible. To test this hypothesis, a series of microgravity experiments of concurrent-flow flame spread over samples of ultra-low area densities are conducted using NASA Glenn Research Center’s Zero Gravity Research Facility (the 5.18 s drop tower). The tested samples are cellulose-based materials of various area densities, ranging from 0.2 mg/cm2 to 13 mg/cm2, as low as one order of magnitude less than those ever tested before. Each sample is 30 cm long by 5 cm wide and is burned in a low-speed concurrent air flow (5 to 30 cm/s). The results show that the concurrent flame spread rate is proportional to the flow velocity relative to the flame and is inversely proportional to the sample area density. A theoretical formulation, provided in this work, suggests that the flame length has a linear relationship with the relative flow speed and has no direct dependency on the sample area density. The experimental data supports this conclusion. From the images recorded in the experiments, a unique flame base tubular structure directed upstream away from the burnout zone is observed for thin samples. This structure is suspected to be due to flame stretching and localized blowoff caused by the oxidative pyrolysis Stefan flows at the sample burnout. This can be an indication that the chemical time becomes comparable to the flow time of the Stefan flow and the tested samples are approaching the kinetically-limited thickness. For the thinnest tested sample (0.2 mg/cm2), flames with concurrent and opposed dual natures are observed when the air flow rate is low (< 20 cm/s). At the lowest tested flow rate (5 cm/s), the flame spread rate exceeds the air flow rate and the flame transits to an opposed flame in the concurrent flow. The dual nature and flame transition are presented and discussed. This study provides detailed examination through high-resolution images of the transition between the concurrent to opposed flame spread modes.

Removing constant‐induced errors in stochastic circuits

Stochastic computing (SC) computes with probabilities using randomised bit-streams and standard logic circuits. Its major advantages include ultra-low area and power, coupled with high error tolerance. However, due to its randomness features, SC's accuracy is often low and hard to control, thus severely limiting its practical applications. Random fluctuation errors (RFEs) in SC data are a major factor affecting accuracy, and are usually addressed by increasing the bit-stream length N . However, increasing N can result in excessive computation time and energy consumption, counteracting the main advantages of SC. In this work, the authors first observe that many SC designs heavily rely on constant inputs, which contribute significantly to RFEs. They then investigate the role of constant inputs in SC and propose a systematic algorithm constant elimination algorithm for suppression of errors to eliminate the constant-induced RFEs by introducing memory elements into the target circuits. The resulting optimal modulo-counting (OMC) circuits remove all constant inputs and, at the same time, minimise RFEs. Analytical and experimental results are presented demonstrating other aspects of OMC circuits, including their initialisation and autocorrelation properties, as well as their optimality in terms of minimising RFEs.

Bespoke Processors for Applications with Ultra-Low Area and Power Constraints

This article makes the case for bespoke processor design, an automated approach that tailors a general-purpose processor IP to a target application by removing all gates from the design that can never be used by the application. The resulting processors are more area- and energy-efficient without sacrificing performance.

Measurement of Electrical Impedance and P-wave Velocity of a Low Permeable Sandstone Core During the Displacement of Saturated Brine by CO2 Injection

Evaluating and monitoring the CO2 behavior in the reservoir, understanding the mechanism of CO2 flow and distribution in the water-CO2 mixture state is essential. In this study, measurement of the complex electrical impedance (Z) and P-wave velocity (Vp) is conducted during the CO2 injection into the rock core under the reservoir condition. Specimen is low permeable sandstone and injection rate is ultra-low (in the low capillarity number (Cn) area) to high. In addition to measuring Z and Vp, differential pressure on the both sides of the specimen and CO2 saturation (SCO2) of the entire specimen are measured. The change of Z and Vp are observed according to the change of differential pressure and SCO2. After the injection test, SCO2 in cross-section of the specimen is estimated using Archie's law and Gassmann's equation (Patchy saturation model) to the experimental results.

Bespoke Processors for Applications with Ultra-low Area and Power Constraints

A large number of emerging applications such as implantables, wearables, printed electronics, and IoT have ultra-low area and power constraints. These applications rely on ultra-low-power general purpose microcontrollers and microprocessors, making them the most abundant type of processor produced and used today. While general purpose processors have several advantages, such as amortized development cost across many applications, they are significantly over-provisioned for many area- and power-constrained systems, which tend to run only one or a small number of applications over their lifetime. In this paper, we make a case for bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application. Since removed gates are never used by an application, bespoke processors can achieve significantly lower area and power than their general purpose counterparts without any performance degradation. Also, gate removal can expose additional timing slack that can be exploited to increase area and power savings or performance of a bespoke design. Bespoke processor design reduces area and power by 62% and 50%, on average, while exploiting exposed timing slack improves average power savings to 65%.

Fast 180° magnetization switching in a strain-mediated multiferroic heterostructure driven by a voltage.

Voltage-driven 180° magnetization switching provides a low-power alternative to current-driven magnetization switching widely used in spintronic devices. Here we computationally demonstrate a promising route to achieve voltage-driven in-plane 180° magnetization switching in a strain-mediated multiferroic heterostructure (e.g., a heterostructure consisting of an amorphous, slightly elliptical Co40Fe40B20 nanomagnet on top of a Pb(Zr,Ti)O3 film as an example). This 180° switching follows a unique precessional path all in the film plane, and is enabled by manipulating magnetization dynamics with fast, local piezostrains (rise/release time <0.1 ns) on the Pb(Zr,Ti)O3 film surface. Our analyses predict ultralow area energy consumption per switching (~0.03 J/m2), approximately three orders of magnitude smaller than that dissipated by current-driven magnetization switching. A fast overall switching time of about 2.3 ns is also demonstrated. Further reduction of energy consumption and switching time can be achieved by optimizing the structure and material selection. The present design provides an additional viable route to realizing low-power and high-speed spintronics.

An on-chip sensor to measure and compensate static NBTI-induced degradation in analog circuits

Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to dynamic switching and high packaging density of SoC) and constant DC bias, there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous, intermittent or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins and/or employing adaptive body bias and dynamic voltage scaling calibration techniques using on-chip sensors or monitors. We propose an ultra low power and low area on-chip NBTI sensor which can be used to accurately sense the NBTI degradation in analog circuits. We have shown that the temporal degradation of PMOS transistor in analog circuits has high correlation to the output variation in proposed NBTI sensor. We also propose a simple circuit for generating accurate body bias to compensate temporal NBTI. We have demonstrated how using the proposed sensor and the adaptive body bias mechanism can be used to compensate NBTI degradation in various analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.

Ultra-long-haul 112 Gb/s PM-QPSK transmission systems using longer spans and Raman amplification

Ultra-long-haul transmission at distances greater than 10,000 km is investigated for 112 Gb/s PM-QPSK signals using span lengths of 75 km and 100 km and all-Raman amplification. Two different ultra-low loss and large effective area optical fibers are studied. We demonstrate a reach length of 10,200 km for a 40 channel system using a fiber with effective area 112 μm(2) with 100 km spans, and a reach length of 13,288 km for a system with 75 km spans using a fiber with effective area of 134 μm(2).

Novel Design Method for Single-Mode Bend-Insensitive Fiber Appropriate for Fiber-to-the-Home Application

A proposal for a new single-mode optical fiber design technique with ultra-low bending loss applicable in fiber-to-the-home operation is presented. The suggested design method is based on reverse problem engineering, which evaluates the refractive index profile. The most remarkable feature of this methodology is designing a bend-insensitive fiber without core radius and mode field diameter reductions. The designed structures exhibit ultra-low bending loss and high effective area simultaneously. Meanwhile, the residual stress of the designed structures is small due to gradual variation of the refractive index in the core region. Simulation results show a bending loss of 4.3 × 10−4 dB/turn at 1.55 μm for a single turn of 5-mm radius.

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123mm2, power: 72mW) or a faster, tinier and even lower power ADC (area: 0.21mm2, power: 25mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.

High-speed liquid chromatography on cadmium-modified silica gel

A novel procedure for the preparation of low-surface-area porous silica adsorbents, modified by cadmium salts, is described. The salt is introduced concurrently with a reduction of the surface area of an inexpensive silica gel by hydrothermal treatment. The resulting materials contain mg/g amounts of the metal. Liquid chromatography on the cadmium-modified adsorbent is shown. Charge-transfer chromatography is favored when the salt is introduced at high hydrothermal temperature which yields ultra low surface area and dense cadmium population.