Ultra Large Scale Integration Devices Research Articles

Electronic Structure Shift of Deeply Nanoscale Silicon by SiO2 versus Si3N4 Embedding as an Alternative to Impurity Doping

Conventional impurity doping of deep nanoscale silicon (dns-Si) used in ultra large scale integration (ULSI) faces serious challenges below the 14 nm technology node. We report on a new fundamental effect in theory and experiment, namely the electronic structure of dns-Si experiencing energy offsets of ca. 1 eV as a function of SiO$_2$- vs. Si$_3$N$_4$-embedding with a few monolayers (MLs). An interface charge transfer (ICT) from dns-Si specific to the anion type of the dielectric is at the core of this effect and arguably nested in quantum-chemical properties of oxygen (O) and nitrogen (N) vs. Si. We investigate the size up to which this energy offset defines the electronic structure of dns-Si by density functional theory (DFT), considering interface orientation, embedding layer thickness, and approximants featuring two Si nanocrystals (NCs); one embedded in SiO$_2$ and the other in Si$_3$N$_4$. Working with synchrotron ultraviolet photoelectron spectroscopy (UPS), we use SiO$_2$- vs. Si$_3$N$_4$-embedded Si nanowells (NWells) to obtain their energy of the top valence band states. These results confirm our theoretical findings and gauge an analytic model for projecting maximum dns-Si sizes for NCs, nanowires (NWires) and NWells where the energy offset reaches full scale, yielding to a clear preference for electrons or holes as majority carriers in dns-Si. Our findings can replace impurity doping for n/p-type dns-Si as used in ultra-low power electronics and ULSI, eliminating dopant-related issues such as inelastic carrier scattering, thermal ionization, clustering, out-diffusion and defect generation. As far as majority carrier preference is concerned, the elimination of those issues effectively shifts the lower size limit of Si-based ULSI devices to the crystalization limit of Si of ca. 1.5 nm and enables them to work also under cryogenic conditions.

Selective Heating of Transition Metal Usings Hydrogen Plasma and Its Application to Formation of Nickel Silicide Electrodes for Silicon Ultralarge-Scale Integration Devices

We developed an apparatus for producing high-density hydrogen plasma. The atomic hydrogen density was 3.1 × 1021 m?3 at a pressure of 30 Pa, a microwave power of 1000 W, and a hydrogen gas flow rate of 10 sccm. We confirmed that the temperatures of transition-metal films increased to above 800。C within 5 s when they were exposed to hydrogen plasma formed using the apparatus. We applied this phenomenon to the selective heat treatment of nickel films deposited on silicon wafers and formed nickel silicide electrodes. We found that this heat phenomenon automatically stopped after the nickel slicidation reaction finished. To utilize this method, we can perform the nickel silicidation process without heating the other areas such as channel regions and improve the reliability of silicon ultralarge-scale integration devices.

Deposition of a Continuous and Conformal Copper Seed Layer by a Large-Area Electron Cyclotron Resonance Plasma Source with Embedded Lisitano Antenna

To deposit copper seed layer on ultra large scale integration devices, a large-area (O 378 mm) electron cyclotron resonance plasma has been generated by using permanent magnets-embedded Lisitano antenna. The plasma source operates in the pressure range of 0.2–1.5 mTorr with microwave power range of 500–2,000 W. By using a Langmuir probe, the electron density and temperature have been measured near the DC sputter target position. Measurements indicate argon plasmas having electron densities of ~5 × 1010/cm and electron temperatures of 5 eV with 750 W microwave power at gas pressures of 0.5 mTorr. Using this plasma source and a DC sputter, we obtained excellent conformal copper seed layer with high aspect ratios of 12:1. This is in contrast with conventional methods using magnetron sputter, which has aspect ratios of 2–3:1. Also, improvements are observed in the smoothness (root mean square roughness of 1.345 nm), uniformity (2.5 % at 300 mm wafer), and sidewall symmetricity (more than 95 %) of the copper seed layer.

Magnetic performance and corrosion resistance of cobalt based magnetic films

To optimise the composition of magnetic materials applied in the fabrication of ultralarge scale integration (ULSI) devices and microelectromechanical systems (MEMS), the magnetic performance and anticorrosion property of cobalt based magnetic films (CoWP, CoPtP and CoMoP) were investigated using vibration sample magnetometer (VSM) and electrochemical technologies (potentiodynamic polarisation curve and electrochemical impedance spectroscopy). Results indicate that CoWP has a small coercivity (592·73 Oe) and large saturation magnetisation value (144·20 emu.g−1); while CoPtP and CoMoP films are hard magnetic materials with coercivity of 1786·57 and 2745·20 Oe, saturation magnetisation value of 91·72 and 120·74 emu.g−1 respectively. Electrochemical measurements reveal the order of corrosion resistance in 3·5%NaCl solution was CoPtP film>CoWP film>CoMoP film. In the fabrication of ULSI devices and MEMS, CoPtP film was recommend to be one of the most suitable magnetic materials. CoPtP film was thick with finer grains (52–78 nm) and lower roughness (18·212 nm).

Material design of plasma-enhanced chemical vapour deposition SiCH films for low-k cap layers in the further scaling of ultra-large-scale integrated devices-Cu interconnects

Cap layers for Cu interconnects in ultra-large-scale integrated devices (ULSIs), with a low dielectric constant (k-value) and strong barrier properties against Cu and moisture diffusion, are required for the future further scaling of ULSIs. There is a trade-off, however, between reducing the k-value and maintaining strong barrier properties. Using quantum mechanical simulations and other theoretical computations, we have designed ideal dielectrics: SiCH films with Si–C2H4–Si networks. Such films were estimated to have low porosity and low k; thus they are the key to realizing a cap layer with a low k and strong barrier properties against diffusion. For fabricating these ideal SiCH films, we designed four novel precursors: isobutyl trimethylsilane, diisobutyl dimethylsilane, 1, 1-divinylsilacyclopentane and 5-silaspiro [4,4] noname, based on quantum chemical calculations, because such fabrication is difficult by controlling only the process conditions in plasma-enhanced chemical vapor deposition (PECVD) using conventional precursors. We demonstrated that SiCH films prepared using these newly designed precursors had large amounts of Si–C2H4–Si networks and strong barrier properties. The pore structure of these films was then analyzed by positron annihilation spectroscopy, revealing that these SiCH films actually had low porosity, as we designed. These results validate our material and precursor design concepts for developing a PECVD process capable of fabricating a low-k cap layer.

Crystal Plasticity Analysis of Dislocation Accumulation in ULSI Cells with Consideration of Temperature Dependence of the Lattice Friction Stress for Silicon

Representative length scale of ULSI (Ultra Large Scale Integration) cells is going to be at a nano-meter order, and the atomic level defects, such as uneven oxide films or dislocation accumulation are becoming more and more important. Among these defects, dislocation accumulation is known to be caused by thermo-plastic deformation in silicon during the processes of device fabrication. In this study, we analyse such thermal stress, plastic slip deformation and accumulation of dislocations in STI (Shallow Trench Isolation) type ULSI devices when the temperature drops from the initial at 1000 °C to room temperature. For the analysis, we use a crystal plasticity analysis code CLP, assuming that lattice friction stress for the movement of dislocations is proportional to the hardness of silicon, which is known to have strong dependency on temperature. The results show that dislocations are generated between the temperature range from 880 to 800 °C, and its maximum density is highly dependent on the lattice friction stress in the temperature range above 800 °C. For example, the difference of 16 MPa in the lattice friction stress at 1000 °C caused increase in dislocation density more than ten times. It is concluded that control of lattice friction stress at high temperatures is one of the most promising way for the suppression of dislocation accumulation.

Excellent Electrical Characteristics of Praseodymium Oxide Dielectrics on Si Substrate by Reactive RF Sputtering

Praseodymium oxide film was grown on Si substrate by reactive RF-sputtering from a Pr target for TaN metal gate. We found that Pr2O3 gate dielectric with TaN metal gate annealed at 700 o C exhibits a higher capacitance value and lower flatband voltage in C-V curves, and shows the leakage value of ~5x10-7 A/cm2 at a bias of 2 V. This Pr2O3 gate dielectric appears to be very promising for future ultra-large scale integration devices.

Characterization of neutral beam source based on pulsed inductively coupled discharge: Time evolution of ion fluxes entering neutralizer

Low-energy neutral beam sources are very promising candidates for realization of next generation ultralarge-scale integrated devices. The use of pulsed inductively coupled plasma and surface (wall) neutralizer appears to be an efficient way of producing high-flux low-energy neutral beams. Measurement of the time evolution of ion fluxes entering the neutralizer plays an essential role in understanding and control of these neutral beam systems. Here the authors present a simple method for measuring the temporal dynamics of ion fluxes in neutral beam source described elsewhere [S. Samukawa et al., J. Vac. Sci. Technol. A 20, 1566 (2002)]. The method is based on the use of a low aspect ratio orifice in the center of neutralizer, magnetic filter, and Faraday cup. At some conditions, it allows (1) to measure the magnitudes of positive and negative wall ion fluxes in pulsed plasmas with an extremely high temporal resolution (better than 1μs) and (2) to examine the difference in surface neutralization between positive and negative ions. The measurements show that neutralization of hyperthermal ions is mainly controlled by geometry of plasma sheath adjacent to the surface neutralizer; however, negative ions are neutralized more easily than positive ones. The experimental results for SF6 (ion-ion) and Ar plasmas in combination with dc/rf bias are reported.

Optical diagnostics for plasma-surface interaction in CF4∕Ar radio-frequency inductively coupled plasma during Si and SiO2 etching

Highly selective etching of SiO2 over Si is central to the manufacture of ultralarge scale integration devices; the process is generally one of reactive ion etching using polymerizing fluorocarbon chemistry. A number of species including electrons, ions, and radicals are generated by reactions in the gas phase and on the surface in the plasma process. A large number of highly reactive fluorine atoms, fluorocarbon radicals, and ions interact with the substrate and produce etch products. These etch products, primarily SiF4 and SiF2, diffuse back into the bulk plasma where they are dissociated and ionized by interactions with electrons, and the resultant products are transported and redeposited onto the substrate and/or wall surface. That is, the plasma structure may differ depending on whether the Si (or SiO2) surface has been exposed to etching or not. Hence, it is essential to investigate the spatiotemporal characteristics of the plasma structure during etching. In this study, measurements of plasma structure during Si or SiO2 etching in CF4∕Ar radio-frequency inductively coupled plasma (rf-ICP) were performed using computerized tomography of optical emission spectroscopy to investigate plasma-surface interactions. We focused on the characteristics of etch products, their daughter products, and the etchant in the gas phase during Si and SiO2 etching in CF4∕Ar rf-ICP and the disturbance of the plasma structure at high amplitudes of LF bias.

Electrical resistivity of polycrystalline Cu interconnects with nano-scale linewidth

The maximum electrical conductivities in polycrystalline Cu interconnects with sub-100nm linewidth were extrapolated from the measured resistivities of the Cu interconnects with various linewidths (100–1000nm) using a Mayadas–Shatzkes (MS) model. These polycrystalline Cu interconnects with TiN cap layers were fabricated by the focused ion beam technique. The scattering parameters by the surface and grain boundary, which were needed to extrapolate the resistivities of the sub-100nm Cu interconnects (using the MS model), were determined to be zero and 0.5, respectively. The result suggested that the grain boundary scattering primarily increased the resistivity of the polycrystalline Cu interconnects. We concluded that large grained Cu interconnects and ultrathin barrier layers were essential to realize low resistance nano-scale Cu interconnects in the future ultralarge scale integration devices.

Dependence of Structural and Electrical Properties on Substrate Temperature for Annealed C54 TiSi2 Thin Films Grown on p-Si Substrates

Substrate temperature effects on the structural and electrical properties of annealed C54 TiSi2 thin films grown on p-Si (100) substrates using a sputtering method were determined with the objective of improving the properties of the films. The results of scanning electron microscopy, energy-dispersive X-ray fluorescence, and X-ray diffraction measurements showed that the thickness of the C54 TiSi2 thin films increases with increasing substrate temperature and that the sheet resistance decreases with increasing substrate temperature up to 200°C. These results indicate that the structural and electrical properties of annealed C54 TiSi2 thin films grown on p-Si (100) substrates using a sputtering method can be improved by increasing substrate temperature, and that these films grown on p-Si(100) substrates using a high-temperature sputtering method hold promise for potential applications in Si-based ultralarge-scale integration devices.

First-principle dynamical electronic characteristics of Al electromigration in the bulk, surface, and grain boundary

Formulas for the driving force of electromigration have been presented using concepts of the tension density, the external force density, and the effective charge tensor density. The ``dynamic'' wind charge tensor density $Z{\ensuremath{\downdownarrows}}_{a\mathrm{dynamic}\mathrm{}\mathrm{wind}}(\mathbf{r})$ has been revealed over and above the conventional ``static'' wind charge tensor density $Z{\ensuremath{\downdownarrows}}_{a\mathrm{static}\mathrm{}\mathrm{wind}}(\mathbf{r}).$ We have demonstrated the application of the concepts to electromigration reliability problems of ultralarge-scale integration devices where extremely high current densities should be maintained through ultrathin film interconnects. Quantum mechanical wave-packet propagation of an Al atom has been examined in some models of thin Al lines which contain atomic defects, using the first-principle electronic structure calculations under the periodic boundary condition. The dynamical electronic properties by our simulation have demonstrated the characteristic features of the $Z{\ensuremath{\downdownarrows}}_{a\mathrm{dynamic}\mathrm{}\mathrm{wind}}(\mathbf{r})$ in the course of the Al electromigration in the bulk, surface, and grain boundary.

Effect of deuterium postmetal annealing on the reliability characteristics of an atomic-layer-deposited HfO2/SiO2 stack gate dielectrics

The characteristics of atomic-layer-deposited (ALD) HfO2(30 Å)/SiO2(10 Å) stacks gate dielectrics were investigated after annealing in a deuterium (D2) ambient. Compared with oxides annealed in a forming gas containing hydrogen (H2), the stack dielectrics annealed in D2 ambient exhibited various advantages such as less charge trapping, less generation of interface state density (Dit), a larger charge-to-breakdown (Qbd), and longer time-dependent dielectric breakdown characteristics under conditions of electrical stress. The improved reliability can be attributed to the strength of the deuterium bond. This deuterium postmetal annealing of a high-k gate dielectric has considerable potential for future use in ultralarge-scale integration device applications.

Electrical conductivity of sidewall-deposited fluorocarbon polymer in SiO2 etching processes

High-aspect-ratio SiO2 contact hole etching is one of the key processes in the fabrication of ultralarge scale integration devices. However, there are many serious problems, such as charge-build-up damage, etching-stop, and microloading effects. Charge accumulation in high-aspect-ratio contact holes during etching is one of the main causes of these problems. In SiO2 etching using fluorocarbon gases, it is well known that a fluorocarbon film is deposited on the underlayer surface and sidewall of contact holes. It is also predicted that an increase in the conductivity of the fluorocarbon film deposited on the SiO2 sidewall markedly reduces the charging potential in the high-aspect-ratio contact holes because of the high conductivity of the deposited polymer. To clarify these phenomena, it is necessary to obtain quantitative measurements of the conductivity of the sidewall surfaces in contact holes. Therefore, we fabricated the sensing device using semiconductor production technology, and monitored sidewall current of SiO2 contact holes on the silicon wafer. The relationship between the chemical structure and sidewall current of the fluorocarbon films deposited in contact holes is investigated. We have found that highly cross-linked and unsaturated fluorocarbon polymer causes high sidewall conductivity in SiO2 contact holes. It is suggested that the deposited fluorocarbon film reduces the charging potential during the SiO2 etching process.

MOCVD of titanium dioxide on the basis of new precursors

Thin films with a considerably higher dielectric constant than silicon dioxide, for example titanium dioxide or titanium containing barium strontium titanate, can be used for dielectrics in ultralarge scale integration devices. TiO2 shows, besides its high dielectric constant, a sufficiently low leakage current and high breakdown field strength. MOCVD is the most promising method for depositing those dielectrics because of its obvious advantages like homogeneity of films, good step coverage and ultrathin film deposition. In this work, three new precursor chemicals have been developed and tested in a low pressure horizontal cold wall-type furnace. For the synthesis of the novel precursors, commercial titaniumisopropylate is brought to an reaction with an alcoholic compound at 150 °C and distilled under vacuum. The motivation for the development of new Ti precursors lies in an improvement of the handling and deposition characteristics as for example the hydrolytic stability. For the three precursors the deposition parameters temperature, pressure, gas flow and activation energy is presented. The electrical properties dielectric constant and leakage current were compared to commercially available titaniumisopropylate.

The Simulation of Copper Drift in SiO2 during Bias Temperature Stress (BTS) Test

AbstractIn order to develop a reliable interconnect integration scheme by using Cu in ultra large scale integrated devices (ULSI), the evolutions of the concentration profile of copper ions in SiO2 was simulated under bias temperature stress (BTS) test. Diffusion equation was solved numerically in two electric field modes. One is constant electric field mode where copper drift was simulated with the assumption that electric field is constant within SiO2 film. In variable electric field mode, simulation was carried out considering the variation of electric field in SiO2 due to copper ions. The diffusion of copper ions in variable electric field mode is slower than that in constant electric field mode, because copper ions in SiO2 reduce electric field near the interface between Cu and SiO2. Flatband voltage shift ) (ΔVFB increases parabolically as BTS time increases in constant electric field mode. However, it has linear relation with BTS time in variable electric field mode, which is typically observed in experiments.

Self-Aligned Passivated Copper Interconnects: A Novel Technique for Making Interconnections in Ultra Large Scale Integration Device Applications

AbstractWe have developed a technique to grow self-aligned epitaxial Cu/MgO films on Si (100) using Pulsed Laser Deposition Method. In this method we deposit a uniform film of Cu/Mg (5-7%) alloy over Si (100) at room temperature using TiN as an intermediate buffer layer. As a result of HRTEM (with spatial resolution of 0.18 nm) and STEM-Z investigations we observed that when this film is annealed at 500°C (in a controlled oxygen environment), in less than 30 minutes time, all the Mg segregates at the top and at the bottom surface of Cu. This is understood to be the consequence of lower surface energy of Mg. At 500°C Mg is quite sensitive to oxygen and thin layer of MgO is immediately formed at the top surface, we also observed a thin layer of MgO at the Cu/TiN interface. Thickness of the upper MgO layer was found to be 15 nm while that of lower layer was 10 nm. MgO underneath layer acts as a diffusion barrier and inhibits the diffusion of Cu in the system. Upper MgO layer acts as a passivating layer and improves the quality of copper against oxidation. Electrical resistivity measurements (in the temperature range 12-300 K) showed MgO/Cu/MgO/TiN/Si (100) sample to be highly conducting. We also observed that the resistivity of the system is insensitive to ambient oxygen environment. Selfaligned MgO (100) layer also provides a means to grow several interesting materials over it. This technique can be used to integrate high temperature superconductors like YBa2Cu3O7 with silicon chip.

Locally delineating of junctions and defects by local cross-section electron-beam-induced-current technique

The local cross-section electron-beam-induced-current (EBIC) technique together with a focused ion beam (FIB) for cross-sectional viewing is discussed. The cross-section formed by FIB treatment on the ultra-large scale integrated (ULSI) device surface maintains sufficient electrical insulation between every node (including the PN junction). This was confirmed in advance using a test structure and an actual ULSI chip. High-resolution EBIC images could be obtained for some samples by irradiating a low-energy electron beam onto the FIB cross-section. This local cross-sectional EBIC technique is very useful for delineating PN junctions and pointing out defect portions upon the failure of ULSI devices. Furthermore, we found that the floating well, which was not connected to the outside electrode, was visualized by thinning the back (∼1 μm) of the cross-section with a FIB. It was clarified by electromotive current simulations that this phenomenon originates in the change in potential of the well due to the staying of the generated carriers which could not diffuse. This application is also very useful for the delineation of multiple well structures in ULSI devices.

Plasma enhanced chemical vapor deposition Si-rich silicon oxynitride films for advanced self-aligned contact oxide etching in sub-0.25 μm ultralarge scale integration technology and beyond

We intentionally introduced excessive Si during the SiOxNy film deposition in order to increase the etch selectivity-to-SiOxNy for advanced self-aligned contact (SAC) etching in sub-0.25 μm ultralarge scale integration devices. The SiOxNy layer was deposited at a conventional plasma enhanced chemical vapor deposition chamber by using a mixture of SiH4, NH3, N2O, and He. The gas mixing ratio was optimized to get the best etch selectivity and low leakage current. The best result was obtained at 10% Si–SiOxNy. In order to employ SiOxNy film as an insulator as well as a SAC barrier, the leakage current of SiOxNy film was evaluated so that SiOxNy may have the low leakage current characteristics. The leakage current of 10% Si–SiOxNy film was 7×10−9 A/cm2. Besides, the Si-rich SiOxNy layer excellently played the roles of antireflection coating for word line and bit line photoresist patterning and sidewall spacer to build a metal–oxide–semiconductor transistor as well as a SAC oxide etch barrier. The contact oxide etching with the Si-rich SiOxNy film was done using C4F8/CH2F2/Ar in a dipole ring magnet plasma. As the C4F8 flow rate increases, the oxide etching selectivity-to-SiOxNy increases but etch stop tends to happen. Our optimized contact oxide etch process showed the high selectivity to SiOxNy larger than 25 and a wide process window (⩾5 sccm) for the C4F8 flow rate. When the Si-rich SiOxNy SAC process was applied to a gigabit dynamic random access memory of cell array, there was no electrical short failure between conductive layers.

Effects of Denudation Anneal of Silicon Wafer on the Characteristics of Ultra Large-Scale Integration Devices

The effectiveness of denudation annealing at high temperatures on the characteristics of ultra large-scale integration (ULSI) devices has been studied. The secondary-ion mass spectroscopy (SIMS) profile showed that the oxygen atoms near the wafer surface diffuse out during the denudation anneal and the amount of outdiffused oxygen atoms increases with the increase of denudation annealing temperature. The depth of the defect-free zone (DFZ) at the surface region, the breakdown property of the thin gate oxide of 7 nm thickness and the leakage current of PN junction diodes were greatly improved following by the denudation annealing process at a high temperature. It is found that the refresh properties of a 256 Mbit dynamic random-access memory (256 M-DRAMs) were closely related to the depth of the DFZ at the device surface and were improved by the denudation annealing. Therefore, denudation annealing at high temperatures is effective for the fabrication of reliable quarter-micron level DRAM devices.