Typical Phase-locked Loop Research Articles

Stability simulation and improvement of typical phase-locked loop of STATCOM with different equivalent grid R/L ratios

Transient synchronization stability is the precondition for dynamic reactive power compensation of STATCOMs in the event of a grid fault, which might be so serious that their neighboring distributed power generators lose their synchronization stability. However, there are very limited research publication in this area. This paper focuses on STATCOM synchronization stability and its improvement. The proposed adaptive phase locked loop (PLL) is based on the estimated phase error rather than the estimated frequency error, which is an innovative approach not yet been seen in published papers. Moreover, the impacts of short-circuit ratio and the ratio of equivalent grid R to X are also investigated. Both steady-state analysis and time-domain simulation results are presented in this paper. The results show good consistency between steady-state analysis, simulation with a controlled current source model and with a detailed STATCOM model, and the differences are within reasonable range. Compared with the typical PLL, the proposed adaptive PLL demonstrates improved performance of transient synchronization stability.

A D-Band Joint Radar-Communication CMOS Transceiver

A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band joint radar-communication complementary metal–oxide–semiconductor (CMOS) transceiver featuring a dual-function mode multiplexer, a power-combining PA with high output power, a current choking high-gain mixer, a two-point modulation (TPM) frequency-modulated continuous-wave (FMCW) digital phase-locked loop (PLL) with a dual-core DCO, and a wideband I/Q local oscillator (LO) generator is implemented in 28-nm CMOS technology. In the radar mode, the RF front end demonstrates 46-GHz bandwidth (BW), and the on-chip PLL/LO generated FMCW chirp achieves a BW of 30 GHz and a slope of 30 GHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{s}$ </tex-math></inline-formula> . In the communication mode, the transceiver including the analog baseband realizes 20-GHz BW, and the image rejection ratio (IRR) is better than 40 dB. The measured transmitter (TX) saturated output power is 13 dBm, and the output 1-dB compression point (OP1dB) is 8.3 dBm. The measured typical PLL phase noise is −111.3 dBc/Hz at a 1-MHz offset from an 11.69-GHz carrier frequency. The TX-to-RX over-the-air (OTA) modulation–demodulation measurement with QPSK and 16-QAM signals shows the error vector magnitude (EVM) of −16.5 and −19.7 dB, respectively.

Robustness Improvement of Single-Phase Inverters Under Weak Grid Cases by Adding Grid Current Feedforward in Delay-Based Phase-Locked Loop

For inverters, a phase-locked loop (PLL) is usually needed for the grid synchronization. Typically, for the single-phase inverters, the orthogonal-signal-generators based PLLs (e.g., delay-based PLL) can be used. However, if the grid at the point of common coupling (PCC) exhibits a large grid impedance, the inverter may not work well or even be unstable. In order to work satisfactorily in the very weak grid, this study aims to formulate a robust PLL. At first, by modeling the inverter output impedance and considering the frequency coupling effect, the stability of the typical delay-based PLL has been analyzed and the reason for the performance degradation has been explained. Then, based on analyzing the differences of PLL blocks under different PCC conditions, the robust PLL with the grid current feedforward is discussed. Compared with the typical PLL, the improvement of the system behaviors in the weak grid cases is mainly attributed to the extra term on the numerator of output impedance, which is introduced by the current feedforward of the proposed PLL. The selection of control parameters has been emphasized for maintaining the high robustness. At last, selected comparative waveforms have verified that the single-phase inverter can perform well even with the large grid impedance, without the grid impedance estimation.

Inertia and Primary Frequency Provisions of PLL-Synchronized VSC HVDC When Attached to Islanded AC System

The islanded scenarios of voltage source converter (VSC) high-voltage DC (HVDC) directly supplying power to islanded loads or connecting to wind farm are becoming popular, in which some new issues are required to be further addressed. While several control strategies have been studied, to the authors’ best knowledge, few have investigated the potential capability of VSC HVDC using the typical phase-locked loop (PLL)-synchronized vector control (PLLSynVC) to address islanded operation issues. To explore the potential capability of the typical PLLSynVC in islanded system, this paper proposes a frequency regulation scheme (FRS), including inertia and primary frequency control, for the PLL-synchronized VSC HVDC based on the motion equation concept. By adding the FRS, the VSC HVDC using the PLLSynVC, similar to a synchronous generator from the view of the phase motion equation, not only can self-maintain the frequency stable in an islanded system, but also naturally avoids the transition of control operation modes without changing the basic control structure. Furthermore, based on the developed phase motion equation, the inertia characteristics of VSC HVDC with the FRS is studied, which synthetically considers the impact of different controllers and PLL, and makes VSC HVDC's manifested inertia clear. The effectiveness of FRS and inertia analysis results is verified by time-domain simulations.

Reduced complexity Kalman filtering for phase recovery in XPIC systems

Reduced-complexity Kalman-based algorithms are proposed to recover the phase of cross-polar interference cancellation (XPIC) receivers in microwave radio relay links. In particular, two completely independent radio frequency (RF) transceiver chains are considered for the two different polarizations, in order to have the maximum flexibility to connect different single carrier transceivers to dual-polarized antennas. A one-state Kalman model is proposed, which is of low complexity and thus suitable for a modern higher data rates M-ary quadrature amplitude modulation (M-QAM) receiver. Moreover, a further reduced complexity version is developed that uses a lower amount of information to recover the phase at the receiver, as well as a downsampling procedure to speed up the Kalman algorithm, and an alternative error computation that is essential to ease the Kalman implementation. It is worth noting that the three last simplifications are general and can be applied not only to a one-state Kalman model. Simulation results compare the proposed simplified Kalman solutions to typical phase-locked loop (PLL) algorithms proving their comparable performance with the benefit of lower complexity. Finally, the relationships between the Extended Kalman and the PLL approaches are investigated. The obtained relation is essential for the cross-polar phase recovery, since, as far as the authors know, there are not closed-form solutions for the PLL parameter optimization in cross schemes.

Timing Jitter Modeling and Minimization for a Servo Track Writer

During servo track writing (STW), the timing jitter in clocking process can induce significant errors on servo pattern, named as phase-in error. In this paper, we measured the timing jitter on our STW experimental setup and modeled the jitter sources in frequency domain. With the timing jitter sources models, the typical phase-locked loop system is looked as a typical closed-loop control system and H2 control method is used to design the loop filter with objective to minimize the timing jitter after the output of voltage control oscillator (VCO). The simulation results show that timing jitter can be significantly reduced with loop filter designed with the H2 method

Bifurcation diagrams and fractal brain boundaries of phase-locked loop circuits

Several 2-parameter bifurcation diagrams and the boundaries of the basin attraction of various periodic orbits associated with a typical phase-locked loop circuit widely used in modern communication systems are presented. Using these diagrams, the authors have identified and confirmed various routes to chaos reported previously for this circuit. Moreover, they have discovered that over certain regions in the parameter space, the circuit is virtually unpredictable over a very long period of time even though it eventually settles down to a periodic steady state. The long transient is manifested in the form of fractal basin boundaries with self-similar structures repeated at any finer scale of resolution. The results implies that if the phase-locked loop (PLL) circuit is operating within the parameter range which resulted in fractal basin boundaries, it will take an extraordinarily long pull-in time to achieve synchronization. The analysis therefore predicts not only the failure boundaries (when the circuit is chaotic), but also a safety margin for design, namely, that one should stay away from fractal basin boundaries.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thresholds and Tracking Ranges in Phase-Locked Loops

This paper presents a general discussion of phase-locked-loop thresholds and tracking ranges. A typical phase-locked loop and its linear equivalent are introduced, and there is a brief discussion of application of the root locus method and the Bode amplitude plot to this circuit. Calculation of the maximum allowable deviation is considered for both phase and frequency modulation (sinusoidal). The SNR threshold is a function of tracking and modulation, and may vary considerably. Threshold behavior-with and without limiting-is discussed, and methods are presented for estimating the threshold in each case. Calculating the tracking range and variation of the tracking range with threshold variation are also discussed. Since an increase in tracking range and a decrease in threshold are obvious design objectives, procedures are given for achieving these goals. After a description of the effects of interference on tracking and the threshold, there is a brief report of a phase-locked-loop intelligibility study conducted by Philco Western Development Laboratories. Appendixes I-IV consider: 1) a phase-locked loop containing an IF amplifier, 2) designing a loop to track Doppler shift only, and 3) improving the SNR by increasing deviation.