TX Insertion Loss Research Articles

A compact low-noise frontend for interleaved Rx/Tx arrays at K-/Ka-Band

AbstractThis contribution deals with a frontend for interleaved receive (Rx)-/transmit (Tx)-integrated phased arrays at K-/Ka-band. The circuit is realized in printed circuit board technology and feeds dual-band Rx/Tx- and single-band Tx-antenna elements. The dual-band element feed is composed of a substrate-integrated waveguide (SIW) diplexer with low insertion loss, a low-noise amplifier (LNA), a bandpass filter, and several passive transitions. The compression properties of the LNA are identified through two-tone measurements. The results dictate the maximum allowable output power of the power amplifier. The single band feed consists of a SIW with several transitions. Simulation and measurement results of the individual components are presented. The frontend is assembled and measured. It exhibits an Rx noise figure of 2 dB, a Tx insertion loss of ~ 2.9 dB, and an Rx/Tx-isolation of 70 dB. The setup represents the unit cell of a full array and thus complies with the required half-wave spacing at both Rx and Tx.

A Hybrid Transformer-Based CMOS Duplexer With a Single-Ended Notch-Filtered LNA for Highly Integrated Tunable RF Front-Ends

A hybrid transformer-based CMOS tunable duplexer with a single-ended blocker-tolerant low-noise amplifier (LNA) is proposed for a highly integrated reconfigurable RF front-end architecture. The proposed LNA adopts $Q$ -enhanced $LC$ notch filter at the source of the cascode device and $LC$ bandpass filter at the load. It improves the blocker tolerance and linearity of the receiver by rejecting unwanted out-of-band blockers and transmitter (TX) leakage signals. The duplexer with the notch-filtered LNA was fabricated in a 65-nm CMOS process. It has a voltage gain of 24.2 dB from the antenna to the LNA output with 28-dB notch filtering, cascaded noise figure of 6.4 dB, TX insertion loss of 3.8 dB, and IIP3FD of 52.4 dBm. It can also cover a mid-band range from 1.6 to 2.2 GHz in cellular applications. It draws an average current of 8 mA from a supply voltage of 1.2 V and has an active area of 1.19 mm2.

A 2.5-GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks

Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7-7.5dB and a Tx insertion loss of 3.9-5.6dB. Self-interference cancellation of >50dB is measured for 20-MHz RF bandwidth in 2.4-2.6-GHz frequency range.

A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-<italic>LC</italic> N-Path LNA

This paper proposes a surface-acoustic wave (SAW)-less tunable RF front end (RF-FE) using an electrical-balance duplexer (EBD) integrated with a switched-LC N-path low-noise amplifier (LNA). The EBD cancels the transmitter–receiver (TX–RX) leakage at the RX frequency by dynamically optimizing the balance of a hybrid transformer, which enables in-band full-duplex (IBFD) operation. A transconductor-based LNA in parallel with a switched-LC N-path network creates input and output notches to reject TX leakage for frequency-division duplexing (FDD) operation. The LNA’s signal-handling capability is enhanced via optimum switch biasing. Fabricated in 0.18- $\mu \text{m}$ SOI CMOS, the RF-FE offers >50-dB tunable rejection from the TX port to LNA output at both TX and RX frequencies, for all 3GPP bands from 0.7 to 1 GHz (i.e., FDD case). It is the first tunable RF-FE including an LNA that achieves +70-dBm TX-path IIP3, and +30-dBm in-band TX power while cancelling the self-interference by >50 dB (i.e., IBFD case). The RF-FE consumes 62.5 mW at 1 GHz with 11.7-dB RX cascaded NF, 3.6-dB TX insertion loss, and 9.62 mm2 active area.

A +25-dBm IIP3 1.7–2.1-GHz FDD Receiver Front End With Integrated Hybrid Transformer in 28-nm CMOS

A highly linear receiver (RX) front end with integrated hybrid transformer (HT) for frequency-division duplexing mobile communications is reported. The HT, implemented with a three-winding coplanar transformer, is used to interface the RX front end with the antenna and the power amplifier. The primary is driven at its center tap with the transmitted signal and at one input with the antenna signal, while the other input is connected to an on-chip programmable balancing impedance. The two secondary drives a differential push–pull common-gate low-noise amplifier (LNA). Assuming a perfectly linear hybrid only 45 dB of transmitter (TX)–RX isolation and 35 dB of common-mode rejection are required to meet the intermodulation specs thanks to the +25-dBm receiver IIP3. This would drastically simplify hybrid balancing and adaptation loop. Cascaded noise figure of duplexer, LNA, and baseband is below 6.7 dB and TX insertion loss below 4.3 dB from 1.7 to 2.1 GHz. The implemented prototype in 28-nm CMOS has an active area of 0.7 mm2 and requires only 26 mW.

Adaptive RF Front-Ends Using Electrical-Balance Duplexers and Tuned SAW Resonators

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE’s frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD’s balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18- $\mu \text{m}$ SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6–3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes.

Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems

An active transmitter (TX) cancellation scheme enabling integration of the antenna interface for frequency division duplex systems is presented. A replica of the TX current is synthesized in shunt with the receiver (RX) by a digital-to-analog converter (DAC). The replica DAC virtually shorts out the TX signal at the RX input while having minimal impact on the TX insertion loss. Propagation of the TX phase noise in the RX band is analyzed and shown to be feed-forward cancelled in the proposed system. A prototype chip including integrated TX, measurement RX, and cancellation circuits, operating on a single-shared antenna, is implemented in 65-nm CMOS. The cancellation replica demonstrates > 50 dB cancellation of a +12.6 dBm peak 20-MHz TX signal across a wide range of center frequencies and up to 5:1 voltage standing-wave ratio at the antenna interface. The RX is able to down-convert the RX signal at 40-MHz offset with < 4.3 dB noise figure degradation in the presence of the residual TX signal.

A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with <1.5:1 voltage standing wave ratio from 1.9 to 2.2 GHz. +70-dBm input-referred third-order intercept point is achieved under high transmitter (TX) power (+30.5 dBm max.). TX IL is <3.7 dB, and receiver IL is <3.9 dB.

Low-Loss Integrated Passive CMOS Electrical Balance Duplexers With Single-Ended LNA

A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky surface acoustic wave (SAW) and bulk acoustic wave (BAW) duplexers in third-generation (3G)/fourth-generation (4G) cellular transceivers. A balancing network creates a replica of the transmitter (TX) signal for cancellation at the input of a single-ended low-noise amplifier (LNA) to isolate the receive path from the TX. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra baluns at the antenna side. The balancing network enables a single-ended LNA with reliable high TX power operation up to 22 dBm by alleviating the common-mode coupling. The duplexer achieves around 50-dB transmitter-receiver (TX-RX) isolation within a 1.6-2.2-GHz range. The cascaded noise figure (NF) of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in a 0.18-μm CMOS process and occupy an active area of 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the asymmetrical topology and stacked techniques, the T/R switch demonstrates ~0.5-dB TX insertion loss, >27-dB TX-RX isolation, and 24.8 dBm IP1 dB across 0.1-1.5 GHz. This brief proposes, for the first time, a CMOS dual-mode PA with an integrated T/R switch for multistandard applications.