Two-step Quantization Research Articles

A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

This paper presents an AC-coupled, incremental analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural recording. It achieves a rail-to-rail electrode DC offset (EDO) rejection, low noise, a small area, and low power consumption. Fabricated in a 180 nm CMOS process, the prototype ADC achieves a high input impedance, 24 mVpp linear input range, and 58.9 dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 12 μW and an area of 0.0192 mm2. The referred-to-input (RTI) noise is 6.9 μVrms within the bandwidth of 1 Hz–10 kHz.

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.

CBREN: Convolutional Neural Networks for Constant Bit Rate Video Quality Enhancement

Constant bit rate (CBR) videos are widely used in streaming playback applications. However, the image quality of the CBR video is often unstable, especially for scenes with large motion. To this end, we design a new model to represent the distortion of High Efficiency Video Coding (HEVC) constant bit rate video, and propose a neural network for a constant bit rate video quality enhancement (CBREN). We propose a dual-domain restoration module (DRM) to jointly learn the prior knowledge in the pixel domain and the frequency domain. To address the degradation resulting from compression, we propose a two-step quantization degradation estimation strategy. The Inverse DCT (IDCT) Translation Unit (ITU) is used to constrain the quantization table of the constant bit rate video to a suitable range, and the Dynamic Alpha Unit (DAU) is used to fine-tune the quantization table according to the content of each frame. In order to effectively reduce the block distortion of different sizes produced in the compression process, we adopt a multi-scale network. Extensive experiments show that our approach can greatly enhance the quality of CBR compressed video. Moreover, our method can also be applied to constant quantization parameter (CQP) video enhancement tasks, and is certainly superior to existing methods.

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta–sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion.

Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme

This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex></formula> 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply.

Combining visual dictionary, kernel-based similarity and learning strategy for image category retrieval

This paper presents a search engine architecture, RETIN, aiming at retrieving complex categories in large image databases. For indexing, a scheme based on a two-step quantization process is presented to compute visual codebooks. The similarity between images is represented in a kernel framework. Such a similarity is combined with online learning strategies motivated by recent machine-learning developments such as active learning. Additionally, an offline supervised learning is embedded in the kernel framework, offering a real opportunity to learn semantic categories. Experiments with real scenario carried out from the Corel Photo database demonstrate the efficiency and the relevance of the RETIN strategy and its outstanding performances in comparison to up-to-date strategies.

Rate Control for H.264 with Two-Step Quantization Parameter Determination but Single-Pass Encoding

We present an efficient rate control strategy for H.264 in order to maximize the video quality by appropriately determining the quantization parameter (QP) for each macroblock. To break the chicken-and-egg dilemma resulting from QP-dependent rate-distortion optimization (RDO) in H.264, a preanalysis phase is conducted to gain the necessary source information, and then the coarse QP is decided for rate-distortion (RD) estimation. After motion estimation, we further refine the QP of each mode using the obtained actual standard deviation of motion-compensated residues. In the encoding process, RDO only performs once for each macroblock, thus one-pass, while QP determination is conducted twice. Therefore, the increase of computational complexity is small compared to that of the JM 9.3 software. Experimental results indicate that our rate control scheme with two-step QP determination but single-pass encoding not only effectively improves the average PSNR but also controls the target bit rates well.

Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC

An architecture for a multibit single-stage delta-sigma analog-to-digital converter (ADC) with two-step quantization is presented. Both the most significant bit and least significant bit signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine dynamic element matching (DEM) and digital-to-analog converter (DAC) is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise shaped by using a digital requantization method. Analysis and behavioral simulation results are presented

Two-step quantization in multibit ΔΣ modulators

An architecture to simplify the circuit implementation of the internal analog-to-digital (A/D) converter in a /spl Delta//spl Sigma/ modulator is proposed. The architecture is based on dividing the A/D conversion into two time steps, which makes the internal quantization feasible with much higher resolution than with conventional solutions. Furthermore, the time steps are interleaved so that the resolution improvement is achieved without sacrificing the speed. It is shown, with a linearized model, that the order of the noise shaping is increased by one with respect to the coarse quantization error made during the first step. For a high oversampling ratio, the coarse quantization error made in the first step is easily suppressed to an insignificant level due to the one order higher noise shaping. Depending on the partitioning of the bits between the conversion steps, the coarse error will dominate below a certain oversampling ratio. However, it is shown that the technique can be extended to more than one order higher noise shaping, making it useful for low oversampling ratios as well.

A Switched-Capacitor Capacitance Bridge Based on the Two-Step Quantization

A Switched-Capacitor Capacitance Bridge Based on the Two-Step Quantization