Two-dimensional Device Simulation Research Articles

Performance Enhancement and Mechanism Analysis of IGZO Thin-Film Transistors Utilizing Interdigital Structure

This study investigates the issue of leakage current reduction in oxide semiconductor thin-film transistors (TFTs) with interdigital structures. Electrical measurements clearly demonstrate that the leakage current of interdigitated IGZO devices decreases as the on/off ratio increases. To explore the reasons behind the reduction in leakage current, we conducted two-dimensional device simulations. The results confirm that the use of interdigital structures can influence the electric field distribution within the device channel, introducing shielding electric fields. As the number of interlayer structures between the source and drain increases, the shielding electric fields proportionally increase. Additionally, interdigitated IGZO devices exhibit a large on/off ratio exceeding 2.7×1010, an ultra-low leakage current of less than 3×10-16 A/μm, and a high saturation mobility of 9.4 cm2/Vs. These findings provide valuable insights for designing low-power, high-performance devices based on IGZO.

The synergistic design of 5 V ESD protection applications using two holding voltage improving methods

In this paper, a series of Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR)-based devices were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS (BCD) process. Two distinct methods, the integration of additional doping regions and current paths, are investigated to improve the proposed devices’ holding voltage (Vh). Two-dimensional device simulation is employed to elucidate the working mechanism of these ESD protection devices, complemented by the introduction of a transmission line pulse (TLP) measuring system to assess their ESD protection capabilities. Comparative analysis of TLP results reveals that both methods contribute significantly to the augmentation of holding voltage in LVTSCR ESD protection devices. The refined structure, LVTSCR_BN, with two additional current paths, surface and buried, demonstrated a noticeable increment in holding voltage. With its holding voltage of 7.619 V and trigger voltage of 10.61 V, LVTSCR_BN is proved suitable for the ESD protection of circuits operating at the voltage of 5 V.

Implementation of Logic Gates Using Drain Engineering Dual Metal Gate-Based Charge Plasma TFET (DE-DMG-CP-TFET)

For digital applications, researchers are exploring the use of Tunnel Field-Effect Transistors (TFETs) as an alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). TFETs offer unique qualities that can be harnessed in digital applications. The presented work focuses on the Drain Engineering Dual Metal Gate based Charge Plasma TFET (DE-DMG-CP-TFET) and its ability to implement various logic functions utilizing 2D device simulations. This simulation refers to employing computational tools to analyze electronic devices in two spatial dimensions, considering parameters such as current-voltage characteristics, electric field analysis, and energy band diagrams. This simulation-based approach enables a comprehensive understanding of the device’s operation under different conditions and facilitates the optimization of its performance. The simulations provide insights into the impact of design parameters, material properties, and device configurations on its functionality. By leveraging the ambipolar nature and gate-controlled tunneling capability of TFETs, compact logic functions can be realized by carefully designing the gate-source overlap and selecting an appropriate silicon body thickness. This research highlights the potential of TFETs in compact logic implementation and demonstrates the value of two-dimensional device simulations in understanding device behavior and optimizing performance. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic operations like OR, AND, NAND and NOR. Using a gate-source overlap (LOV) and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET.

Metal-semiconductor-metal solar-blind ultraviolet photodetector based on Al0.55Ga0.45N/Al0.4Ga0.6N/Al0.65Ga0.35N heterostructures.

We have designed a metal-semiconductor-metal (MSM) solar-blind ultraviolet (UV) photodetector (PD) by utilizing Al0.55Ga0.45N/Al0.4Ga0.6N/Al0.65Ga0.35N heterostructures. The interdigital Ni/Au metal stack is deposited on the Al0.55Ga0.45N layer to form Schottky contacts. The AlGaN hetero-epilayers with varying Al content contribute to the formation of a two-dimensional electron gas (2DEG) conduction channel and the enhancement of the built-in electric field in the Al0.4Ga0.6N absorption layer. This strong electric field facilitates the efficient separation of photogenerated electron-hole pairs. Consequently, the fabricated PD exhibits an ultra-low dark current of 1.6 × 10-11 A and a broad spectral response ranging from 220 to 280 nm, with a peak responsivity of 14.08 A/W at -20 V. Besides, the PD demonstrates an ultrahigh detectivity of 2.28 × 1013 Jones at -5 V. Furthermore, to investigate the underlying physical mechanism of the designed solar-blind UV PD, we have conducted comprehensive two-dimensional device simulations.

A novel robust SCR with high holding voltage for on-chip ESD protection of industry-level bus

In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip.

Device Physics of Vertical Static Induction Transistors

Vertical static induction transistors (SITs), with vertically arranged source, porous gate, and drain electrodes, were proposed in 1950s and have recently gained new attention because of their suitability as flexible substrates and for hybrid integration with light-emitting diodes. However, the understanding of them is hindered by Schottky gate leakage and relies on case-by-case simulations. Here, we derive concise expressions for the channel potential and current-voltage characteristics for ideal SITs, including the subthreshold swing, threshold voltage, and above-threshold region. The theory is verified by two-dimensional device simulation and agrees well with the reported experimental results. An ideal SIT can be approximated as a partially gated transistor in parallel with a resistance and needs a sub-500-nm pore diameter to exhibit sharp switching in transfer scanning and good saturation in output scanning. The proposed theories connect the device structure and electrical characteristics of SITs concisely, and conclusions are also applicable to permeable base transistors.

Device characteristics of the select transistor in a vertical-NAND flash memory

In this paper, variation in the parameters of the select transistor of a vertical-NAND (V-NAND) flash memory device is investigated for device optimization and performance evaluation. Device characteristics including threshold voltage (V TH), subthreshold swing (SS) and off-current (I OFF) are evaluated using two-dimensional device simulation. An equivalent structure of the V-NAND flash memory select transistor is suggested, which includes a fully depleted silicon-on-insulator MOSFET region and a bulk MOSFET region. The effects on device performance of parameter variation of the select transistor are investigated with physical modeling focusing on two merged MOSFET structures. Vertical channel thickness and channel scaling effects on V TH, SS and I OFF are studied. However, the corner shape in the select transistor has a negligible effect on device performance. The simulation results in this work can provide guidance for the design of the select transistor in V-NAND flash memory devices.

Temperature-Independent Current Dispersion in 0.15 μm AlGaN/GaN HEMTs for 5G Applications.

Thanks to high-current densities and cutoff frequencies, short-channel length AlGaN/GaN HEMTs are a promising technology solution for implementing RF power amplifiers in 5G front-end modules. These devices, however, might suffer from current collapse due to trapping effects, leading to compressed output power. Here, we investigate the trap dynamic response in 0.15 μm GaN HEMTs by means of pulsed I-V characterization and drain current transients (DCTs). Pulsed I-V curves reveal an almost absent gate-lag but significant current collapse when pulsing both gate and drain voltages. The thermally activated Arrhenius process (with EA ≈ 0.55 eV) observed during DCT measurements after a short trap-filling pulse (i.e., 1 μs) indicates that current collapse is induced by deep trap states associated with iron (Fe) doping present in the buffer. Interestingly, analogous DCT characterization carried out after a long trap-filling pulse (i.e., 100 s) revealed yet another process with time constants of about 1-2 s and which was approximately independent of temperature. We reproduced the experimentally observed results with two-dimensional device simulations by modeling the T-independent process as the charging of the interface between the passivation and the AlGaN barrier following electron injection from the gate.

Investigation on holding voltage of asymmetric DDSCR with floating heavy doping in 0.18 μm CMOS process

In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found.

Design of high voltage electrostatic protection device for CAN bus

The Dual-Direction Silicon Controlled Rectifier (DDSCR) device has dual-direction electrostatic protection function and strong current discharging ability, which is widely used in ESD on-chip protection. In this paper, a high performance symmetric high voltage Dual-Direction Silicon Controlled Rectifier with floating P+ (HVDDSCR_FP+) is designed for CAN bus under 0.18 μm BCD process. In order to predict and verify the ESD performance of the device, TCAD two-dimensional device simulation and Transmission Line Pulse (TLP) test system were used. The experimental results show that the HVDDSCR_FP + structure has not only symmetrical positive and reverse I-V curves, but also the characteristics of high holding voltage and high failure current. Compared with the traditional HVDDSCR, HVDDSCR_FP+, at 25V forward and reverse trigger voltages (Vt), has increased its holding voltage (Vh) from 12V to 20V, failure current (It2) from 5A to 35A. In the actual tape-out process, it is found that the width of the N-well has a great influence on the performance of the device. After analyzing the reason and improving it, the leakage current of the device is reduced from μA level to nA level.

Novel attributes of a dual pocket tunnel field-effect transistor

In this paper, we propose the application of a dual pocket adjacent to the source in a tunnel field effect transistor (TFET) to improve its electrical characteristics. Using two-dimensional device simulations, we demonstrate that if appropriate doping concentration and length are chosen for the dual pocket, then a sharp curvature is obtained in the energy bands at the onset of tunneling. Consequently, a smaller tunneling width and higher band-to-band tunneling are obtained in a dual pocket TFET (DP-TFET). We demonstrate that the proposed DP-TFET exhibits a 64% smaller average subthreshold swing (SS) compared to a conventional TFET and a 39% smaller average SS compared to a TFET in which a single fully depleted counter-doped pocket adjacent to the source is added. Moreover, the proposed technique of inserting a dual pocket is effective at lower supply voltage (V DD = 0.5 V). Therefore, we can obtain a high ON-current to OFF-current ratio at lower supply voltages and the proposed technique can be employed in future TFETs for low power applications.

A High Performance Normally-Off AlGaN/GaN Split-Gate Metal-Insulator-Semiconductor High Electron Mobility Transistor (MIS-HEMT) Using Piezo Neutralization Technique

In this paper, we propose a novel normally-off MIS-HEMT structure, mainly using Split-Gate Technology, Piezo Neutralization Technique (PNT), Field Plate Technology. By analyzing the effects of different Al composition in the PNT layer and buffer layer on devices, the Piezo Neutralization Technique is optimized. The current turn-on/off is controlled by changing gate voltage to regulate the horizontal conduction band between the double gates. The effects of gate length and block barrier size between the double gates on device performance are studied. Through two-dimensional device simulation, the operation principle and internal mechanism are analyzed. An improved device with good performance is presented. The threshold voltage Vth is 4.1 V, the peak transconductance is 0.3 S/mm, the maximum drain current is 1.1 A/mm and the breakdown voltage is 1200 V.

Mechanism analysis of irradiation location dependent leakage current for zinc oxide thin-film transistors

For large-area electronic applications, the mechanism of the leakage current in oxide-semiconductor thin-film transistors (TFTs) has become a critical issue. In this work, the impact of the irradiation location on the photo-leakage current of zinc oxide (ZnO) TFTs is investigated. The photo-leakage current of the ZnO TFTs is not only dependent on the light irradiation but it is also dependent on the parasitic capacitance between the drain electrode and the floating gate metal. The photo-leakage current of the source-half irradiation TFT is larger than that of the drain-half irradiation TFT. To explain this phenomenon, the profile of the electric potential and the electron concentration is analyzed by two-dimensional device simulation. It is found that the floating gate metal plays the dominant role in the photo-leakage current. This research provides insight into TFT structure optimization and high-performance TFT process development.

A Charge Plasma Based Label Free Biomolecule Detector Using SiGe-Heterojunction Double Gate Tunnel FET

To overcome the random dopant fluctuations (RDFs) and high thermal budget problems faced by normally doped Tunnel Field Effect Transistor (TFET) devices, charge plasma SiGe-heterojunction double gate TFET is utilized to design a label free biosensor. The performance of proposed biosensor is analyzed for different values of dielectric constant (k), charge density (both positive and negative), gate work function and cavity dimensions. These parameters alter the electric properties of the biosensor which help in the detection process. Their effect on the drain current, electric field, surface potential, sub-threshold swing (SS), ION/IOFF ratio, and electron tunneling rate (ETR) of the device is also discussed. Furthermore, the drain current sensitivity of the proposed biosensor is analyzed and it is found that a maximum sensitivity of 1.13 × 1010 is obtained for dielectric constant k = 12. The proposed biosensor is implemented by carrying out two-dimensional device simulations using the Silvaco ATLAS tool.

Floating Body DRAM with Body Raised and Source/Drain Separation

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

PurposeHigh packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.Design/methodology/approachSilicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.FindingsThe proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.Originality/valueGermanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

DC performance analysis of III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon FET circuits with quantum mechanical effects

In this article, the electrical behavior of laterally grown novel short-channel III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) has been studied based on their quantum mechanical effect (QME). Firstly, by varying the device process parameters of the novel TFET structure, the DC parameter responses viz. threshold voltage, electric field and surface potential are investigated. Further these responses are analyzed by considering the QME for better device performance. Two-dimensional numerical device simulator (SILVACO TCAD) tool is used for simulating the quantum and semi-classical models. The simulation work has been validated by extensive analytical modeling, that reflected in our accurate graphical representations. Finally, to investigate the QME effect in circuit level applications, an TFET inverter circuit has been designed and its DC performance viz. power dissipation and propagation delay analysis is performed.

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL).

Extended gate with source splitted tunnel field effect transistor for improved device performance

A novel tunneling field effect transistor having extended gate with source(s) splitted (EG-SS-TFET) is proposed in this paper. The device physics of our proposed structure is compared with conventional L-shaped TFET for better device performance. The vertical band-to-band (B2B) tunneling in L-shaped structure is our motivation, which has been finetuned by gate extension (varied 2 nm to 6 nm) and splitted source (varied 2 nm to 10 nm). The gate extension results better tunneling at source-channel interface. The device models are simulated using two-dimensional numerical device simulator (Silvaco). The turn-on voltage of our proposed EG-SS-TFET is about 0.35 V lower than other established L-shaped TFET structures. The average Subthreshold Swing (SS) is recorded about 10 mV/decade lower than conventional L-shaped TFETs, resulting steep slope for fast switching applications.

Numerical Study of Sub-Gap Density of States Dependent Electrical Characteristics in Amorphous In-Ga-Zn-O Thin-Film Transistors

We demonstrate the effect of the sub-gap density of states (DOS) on electrical characteristics in amorphous indium-gallium-zinc (IGZO) thin-film transistors (TFTs). Numerical analysis based on a two-dimensional device simulator Atlas controlled the sub-gap DOS parameters such as tail acceptor-like states, tail donor-like states, Gauss acceptor-like states, and Gauss donor-like states in amorphous IGZO TFTs. We confirm accuracy by exploiting physical factors, such as oxygen vacancy, peroxide, hydrogen complex, band-to-band tunneling, and trap-assisted tunneling. Consequently, the principal electrical parameters, such as the threshold voltage, saturation mobility, sub-threshold swing, and on-off current ratio, are effectively tuned by controlling sub-gap DOS distribution in a-IGZO TFTs.