Twisted Ring Counter Research Articles

An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs

Monolithic 3-D (M3D) integration offers higher-density integration compared to 3-D integration based on through-silicon vias. Advances in testing are however needed to screen defects in M3D integration without significantly impacting manufacturing cost. We propose a built-in-self-test (BIST) solution to target shorts and opens in interlayer vias (ILVs). In the proposed solution, scan cells at the interface of two layers are stitched into a twisted-ring counter (TRC) using their functional outputs and ILVs. The interface-register cells launch and capture tests, and a test path consists of ILVs and a multiplexer. We map the problem of minimizing the length of the wires added to stitch the TRC to that of finding a minimum-cost Hamiltonian circuit in a weighted bipartite graph. Since the weighted Hamiltonian circuit problem is NP-Complete, we propose a heuristic algorithm for this problem. We also propose a framework based on artificial neural network to carry out diagnosis when a chip fails the proposed test. We show using simulations that the proposed BIST solution can detect all opens and shorts. We also show using simulations that the proposed diagnosis framework can accurately estimate the size of defects in ILVs.

Photonic processing of all‐optical Johnson counter using semiconductor optical amplifiers

This study presents a novel design of Johnson counter using D flip-flops. The performance of D flip-flop is carried out by exploiting the cross-gain modulation effect in semiconductor optical amplifier (SOA), purging the use of components like polarisation controllers, switches and so on. Performance is evaluated in terms of various variants like operational speed, cost effectiveness of design, rise time/fall time, quality of signal received and the system is found to give better results in terms of extinction ratio even without any feedback path. The Johnson counter or twisted ring counter is implemented using three all-optical D flip-flops producing six states. The D flip-flop incorporates travelling wave SOA and all-optical NOT gate. The proposed counter is reasonably valuable as it desires half of the flip-flops in association to other ring counters which directly reduce the cost of the system.

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression

As technology processes scale up and design complexities grow, system-on-chip integration continues to rise rapidly. According to these trends, increasing test data volume is one of the biggest challenges in the testing industry. In this paper, we present a new test data compression method based on reusing a stored set with tri-state coding (TSC). For improving the compression efficiency, a twisted ring counter is used to reconfigure twist function. It is useful to reuse previously used data for making next data by using the function of feedback of the ring counter. Moreover, the TSC is used to increase the range information transmission without additional input ports. Experimental results show that this compression method improves a compression ratio and a test time on both International Symposium on Circuits and Systems’89 and large International Test Conference’99 benchmark circuits in most cases compared to the results of the previous work without a heavy burden on the hardware.

High speed optical 4-bit twisted ring counter using electro-optic effect of Mach-Zehnder interferometer

A 4-bit twisted ring counter is demonstrated utilizing the electro-optic effect of lithium niobate based Mach-Zehnder Interferometer (MZI). The MZI structures working on the principle of electro-optic effect show the powerful ability to switch the optical signal from one output port to the other. The theoretical description along with appropriate mathematical formulation is provided and the proposed device is analysed using beam propagation method. The proposed scheme will be helpful in optical signal processing and packet switching networks.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits. Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.

Scalable Test Generators for High-Speed Datapath Circuits

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.

Modified Twisted-Ring Counter Circuit

In a twisted-ring counter (a feedback shift register in which the next input digit is the complement of the outgoing digit) with three or more stages, the state diagram consists of the desired sequence and other closed sequences composed of unused states. If the counter enters one of the latter, it will not enter the desired sequence. This correspondence points out the minimum modification necessary to ensure that, whatever state the counter is in initially, it will always, in due course, enter the desired sequence. It is shown that the input stage must not be reset unless a group of stages at the opposite end, m in number, are in the 1 state, where m is the smallest integer greater than n/3 and n is the number of stages.

Tunnel Diode-Transistor Twisted Ring Counter

A new tunnel diode-transistor twisted ring counter is described. Each stage of the counter consists of a tunnel diode controlling a long tailed pair which switches current into the following stage. Rectangular input pulses are ``differentiated'' by a shorted delay cable and the tunnel diodes are progressively switched to high voltage states by the positive pulses and then progressively reverse switched to low voltage states by the negative pulses. The scaling capacity of the counter for rectangular input pulses is (2n−1) where n is the number of stages. A maximum scaling rate of 450 MHz was observed for a practical three stage quinary counter.

A 100 MHz twisted ring counter

The paper describes a twisted ring counter employing two gated flip-flops which with appropriate input pulse shaping is capable of operating at input pulse repetition rates in excess of 100 MHz.

A 500 Mc twisted ring counter whose resolution is limited by gate switching speed only

This paper describes a new high-speed counting scheme and circuit obtaining the maximum possible counting frequency with conventional circuit elements.