TFET Research Articles

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET

High speed and low power dissipation devices are expected from future generation technology of Nano-electronic devices. Tunnel field effect transistor (TFET) technology is unique to the prominent devices in low power applications. To minimize leakage currents, the tunnel switching technology of TFETs is superior to conventional MOS FETs. The gate coverage area of different fin shape hybrid tunnel field-effect transistors is more impacted on electric characteristics of drive current, leakage current and subthreshold slope. In this paper design various fin patterns of hybrid TFET devices and shows on better performance as compared with other fin shape hybrid tunnel FET. The TCAD simulation tool is used to determine the characteristics of different fin shape tunnel FET.

Simulation Analysis of Noise Components in NCTFET with Ferroelectric Layer in Gate Stack

Tunnel FETs (TFETs) are a strong contender for replacing conventional MOSFETs in lower power applications due to their low off-state current and sub-threshold swing being much lower than 60 mV/decade. The major trade-off is the shortcomings of TFET, which are ambipolar behaviour, low on-state current and large miller capacitance. The various novel structures of TFETs have been proposed by researchers. This work presents one such structure of heterojunction negative capacitance TFET with raised source and gate material overlapping. With the intervention of the ferroelectric layer in the gate stack of TFET, the overall performance of the device has been improved. Further AC DC analysis and electrical noise analysis are carried out for the proposed device to see the impact of improvisations being done in the structure on the input–output characteristics of the device. Synopsys TCAD tool is used to carry out the simulations at low and high frequencies. As per the results obtained, the raised source device using Ge as source material exhibits a high ION of 4.295 × 10−5 A/μm, low IOFF of 6.01 × 10−15 A/μm and sub-threshold slope of 53.75 mV/decade. The proposed device structure is having least ambipolarity and can be used in ultra-low power circuits.

Ultralow Subthreshold Swing 2D/2D Heterostructure Tunneling Field-Effect Transistor with Ion-Gel Gate Dielectrics

Two-dimensional (2D) transition-metal dichalcogenide (TMD) semiconductors are promising materials for realizing band-to-band tunneling devices owing to the atomically thin layer and abrupt interface of their heterostructures. In this study, we transferred scalable few-atomic-layer thin films using metal-organic chemical vapor deposition (MOCVD)-grown molybdenum disulfide (MoS2) as an n-channel and CVD-grown molybdenum ditelluride (MoTe2) and tungsten diselenide (WSe2) as p-channels to build van der Waals vertical heterostructures. The heterostructures of intrinsic MoS2 and MoTe2 (or WSe2), each having n-type, ambipolar, or high p-type conductivity, were suitable for tunneling field-effect transistor (TFET) applications. We measured the electrical transport properties of the MoS2/MoTe2 (or WSe2) heterostructures using an ion-gel top gate. The fabricated TFET with MoS2/MoTe2 (or WSe2) heterostructures exhibits a subthreshold swing as low as 9.1 (or 7.5) mV/dec. The negative differential transconductance, negative differential resistance, and temperature-dependent I–V characteristics demonstrate the band-to-band tunneling process. The findings have significant potential for applications in the large-area production of next-generation wearable, stretchable, and flexible low-power electronic devices.

Design and Analysis of Charge Plasma-Based Vertical-Nanowire Tunnel FET for Biosensor

In the semiconductor industry, nanoscale devices have better ability to provide for biomolecules detection, but they face various problems during fabrication process, such as high doping concentration, random dopant fluctuation (RDF), higher production cost, low electrostatic control. To overcome these problems, charge plasma (CP) technique has been introduced by the formation of hafnium material at drain side and platinum material at source side with appropriate work-function. The proposed work charge plasma-based vertical-nanowire tunnel FET (CP-VNWTFET) has been designed and analyzed for biosensor application using different dielectric constant and gate underlap method by creating a cavity area under the gate metal. The sensitivity ([Formula: see text]) of biosensor is calculated in terms of change in drain-current ([Formula: see text]) and transconductance ([Formula: see text]) by immobilizing the biomolecules such as Urease, Keratin, Streptavidin, ChOX, Zein, Gluten using gate underlap and dielectric modulation technique. The performance parameters like subthreshold slope (SS), off-current ([Formula: see text]), on-current ([Formula: see text]), on/off current ratio ([Formula: see text]) of the CP-VNWTFET have also been observed while varying the neutral and charged biomolecules at various biased conditions. The device is simulated by using Silvaco ATLAS simulator. The proposed device has been found to be suitable for low power sensor design application.

Multivalley Electron Conduction at the Indirect-Direct Crossover Point in Highly Tensile-Strained Germanium

For applications such as low-power tunneling transistors and memory, lasers, qubits, and spintronics, there is interest in using strain to enhance carrier mobility in semiconductors. This experimental and theoretical study investigates transport in highly strained germanium, in which multivalley electron conduction emerges. Surprisingly, all conduction occurs via the L valley in Ge for biaxial tensile strain below 1.6%, while above the contribution from the \ensuremath{\Gamma} valley increases, with negligible contributions from the underlying strain template.

The effects of source doping concentration and doping gradient on the ON-state current of Si nanowire TFETs

The tunnel field-effect transistor (TFET) is considered a promising next-generation transistor due to its potentially limit-breaking low subthreshold swing and better immunity against short-channel effects. However, the low ON-state current (ION) of TFETs has been a critical problem. In this work, we investigated the effects of the source doping concentration and the source doping gradient (SDG) on the ION of n-type Si gate-all-around (GAA) nanowire (NW) TFETs using an ATLAS device simulator. Unexpectedly, we found that increasing the source doping concentration does not necessarily improve ION, especially for TFETs with a large SDG. Moreover, although reducing the SDG indeed increases ION, for TFETs with low source doping concentration (e.g., 1 × 1019 cm−3), the improvement in ION by reducing the SDG becomes insignificant.

Electric Field and Strain Tuning of 2D Semiconductor van der Waals Heterostructures for Tunnel Field-Effect Transistors.

Heterostacks consisting of low-dimensional materials are attractive candidates for future electronic nanodevices in the post-silicon era. In this paper, using first-principles calculations based on density functional theory (DFT), we explore the structural and electronic properties of MoTe2/ZrS2 heterostructures with various stacking patterns and thicknesses. Our simulations show that the valence band (VB) edge of MoTe2 is almost aligned with the conduction band (CB) edge of ZrS2, and (MoTe2)m/(ZrS2)m (m = 1, 2) heterostructures exhibit the long-sought broken gap band alignment, which is pivotal for realizing tunneling transistors. Electrons are found to spontaneously flow from MoTe2 to ZrS2, and the system resembles an ultrascaled parallel plate capacitor with an intrinsic electric field pointed from MoTe2 to ZrS2. The effects of strain and external electric fields on the electronic properties are also investigated. For vertical compressive strains, the charge transfer increases due to the decreased coupling between the layers, whereas tensile strains lead to the opposite behavior. For negative electric fields a transition from the type-III to the type-II band alignment is induced. In contrast, by increasing the positive electric fields, a larger overlap between the valence and conduction bands is observed, leading to a larger band-to-band tunneling (BTBT) current. Low-strained heterostructures with various rotation angles between the constituent layers are also considered. We find only small variations in the energies of the VB and CB edges with respect to the Fermi level, for different rotation angles up to 30°. Overall, our simulations offer insights into the fundamental properties of low-dimensional heterostructures and pave the way for their future application in energy-efficient electronic nanodevices.

Hetero-gate dielectric SiGe/Si tunnel FET: a hydrogen gas sensor with improved sensitivity

Hetero-gate dielectric SiGe/Si tunnel FET: a hydrogen gas sensor with improved sensitivity

Junctionless tunnel field-effect transistor with a modified auxiliary gate, a novel candidate for high-frequency applications

In this paper, we propose a novel junctionless tunnel field-effect transistor that uses a tunneling gate and a modified auxiliary gate. The first one is employed to enhance the DC/AC performance of the device, and the second one is used to suppress the ambipolar conduction. Due to a uniformly doped Silicon body, dopant diffusion and the formation of abrupt P–N junctions are no longer a big concern. We also illustrate that the fabrication process of heterogate junctionless tunneling field-effect transistor (HJL-TFET) is fully compatible with CMOS technology. Using a calibrated device simulator, the impact of non-idealities such as traps and temperature is thoroughly investigated. The quantum confinement, effect which severely degrades low channel thickness TFETs is also assessed. Furthermore, the impact of ferroelectric material on the transfer characteristics of our device has been studied. Based on the results, HJL-TFET shows desirable parameters such as the ION = 345 μA/μm, SSAVG = 39.34 mV/dec, ION/IOFF = 5.67 × 108, and fT = 225.5 GHz.

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal–oxide–semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less TFETs (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10−6 A and 16.6 mV dec−1, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs.

Potential Sensing Application of Oxygen Gas with Charge Plasma Based Negative Capacitance Tunnel FET

Potential Sensing Application of Oxygen Gas with Charge Plasma Based Negative Capacitance Tunnel FET

Band Alignment in Black Phosphorus/Transition Metal Dichalcogenide Heterolayers: Impact of Charge Redistribution, Electric Field, Strain, and Layer Engineering

The objective of this work is to study the effects of charge redistribution, applied layer-normal electric fields, applied strain, and layer engineering on the band alignment of Black Phosphorus (BP)/Molybdenum disulphide (MoS2) heterostructure through Density Functional Theory (DFT) simulations. Black phosphorus works as a p-type material with high mobility, mechanical flexibility, and sensitivity to number of layers. Combining it with the more electronegative material, MoS2 results in strong carrier confinement and a Type II heterostructure. Charge redistribution among the layers shifts the band alignment expected from the Electron Affinity Rule. Applied external fields, strain and multiple BP layers provide band-alignment tunability within the Type II range and/or, transition to Type I and Type III heterostructures. The tunability in BP/MoS2 heterostructure may be useful as tunnel field effect transistors, rectifier diodes with tunable barrier height, reconfigurable FETs, and electro-optical modulators. Furthermore, considering heterostructures of monolayer BP with other monolayer Transitional Metal Dichalcogenides (TMD) suggests the ability to achieve different band alignment types. In our simulations, a Type I alignment is found with Tungsten diselenide (WSe2), Molybdenum diselenide (MoSe2), and Tungsten disulphide (WS2), and a Type III for Hafnium disulphide (HfS2) and Hafnium diselenide (HfSe2).

Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon–germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 μA can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal–oxide semiconductor devices.

Charge-plasma based symmetrical-gate complementary electron–hole bilayer TFET with improved performance for sub-0.5 V operation

In this paper, the complementary charge-plasma (CP) based symmetrical-gate electron–hole bilayer (EHB) tunnel field-effect transistor (TFET) at a low operating voltage (⩽0.5 V) is introduced. Where, by using CP technique, the source/drain and EHB-channel is induced by depositing metal electrode with appropriate work function. Moreover, the immunity against random dopant fluctuations and the feasibility of a self-aligned process due to a symmetrical top/bottom gate arrangement without the need for a high thermal annealing process make the fabrication of the proposed EHB-TFET very reliable and efficient. Moreover, by implementing the density gradient quantum correction model, the quantum confinement and its effect on confining the 2D electron–hole concentration are also corrected as the proposed device has a smaller channel thickness of 5 nm. The proposed device shows superior performance against almost all Si-based CP-TFETs with a higher ON-current of 47.33 μA μm−1, a smaller average subthreshold swing of 13.53 mV dec−1 and a high ON-current to OFF-current ratio of 2.16 × 1013. This indicates that the proposed device is a promising candidate for future low-power applications.

Vertical GaN/InGaN/GaN heterostructure tunnel field-effect transistor: DC and analog/RF performance

This work reports an [Formula: see text]-type GaN/InGaN/GaN heterostructure vertical double-gate tunnel field-effect transistor (VTFET) using exhaustive calibrated simulation for the first time. Investigation has been done for the proposed structure by including a polarization layer of InGaN near the source-channel junction. From the analysis, it has been observed that after the introduction of polarization layer near the source-channel interface, drain current increases due to the increase in charge concentration (2DEG) near the interface due to inter-band tunneling. Value of 2DEG concentration achieved post introducing the polarization layer is [Formula: see text] [Formula: see text]. The reported structure is optimized using parametric sweep optimization technique. Here, a detailed dc and analog/RF performance estimation has been done for the structure with heterostructure. In-depth sensitivity analysis has been done for the structure with the polarization layer. It is reported that the structure with HfO2 as the dielectric material with [Formula: see text] of 2 nm and with gate metal work function of 5.8 eV gives the optimum performance at 300 K. Further, it demonstrates high cutoff frequency ([Formula: see text] and gain bandwidth product (GBW) as 1000 GHz and 300 GHz, respectively. Hence, the reported structure is a better alternative for high-power steep switching analog and RF applications.

Implementing a Single Gate Heterostructure Tunnel FET as a Low-Power Photosensor with Improved Sensitivity

This work investigates the effectiveness of a single gate SiGe/Si heterostructure tunnel field-effect transistor (SGHTFET) as a photosensor in the visible spectrum. A transparent zinc oxide (ZnO) layer is used as the optical region over the channel for sensing the incident light. When light impinges on the gate catalyst and creates optical charge carriers in the illumination region, the conductance of the device considerably rises and, consequently, the subthreshold current changes. For the suggested photosensor, the effect of varying drain-to-source voltage (VDS), germanium mole fraction (x), and silicon film thickness (tsi) on the sensor performance are investigated. The sensor offers enhanced sensitivity performance as compared to the traditional TFET in terms of several optical figures of merit (FOMs) such as available photocurrent, responsivity, quantum efficiency, sensitivity, and SNR, and can therefore be utilized as an efficient photosensor. The reported sensor has a peak responsivity (R) of 2.23 A W−1 and quantum efficiency (η) of 7.31 at a wavelength (λ) of 450 nm.

A Dual-Drain Vertical Tunnel FET with Improved Device Performance: Proposal, Optimization, and Investigation

In this manuscript, a dual-drain Vertical Tunnel FET structure is proposed and investigated for the first time. The simulation outcomes clearly manifest that reduction in channel thickness, which has inadequate impact on the tunneling region, significantly improves numerous DC parameters of the proposed device including subthreshold swing, on-state current and current-switching ratio by enhancing the band-to-band tunneling of the charge carriers at source/channel interface caused by enlarged electric field. In order to make the proposed device suitable for low power applications, dielectric material is incorporated in between two drain/channel interfaces to reduce the subthreshold leakage current. A detailed investigation is carried out to determine the influence of varying device footprints on various electrical parameters and accordingly, the optimized device performance is achieved. TCAD-based simulation results reveal that a considerably low subthreshold swing of 18 mV decade−1 along with a high current-switching ratio of can be achieved with optimum geometric dimension of design parameters i.e., gate-oxide, source and channel. Further, the performance of the proposed device is compared with various existing TFET structures and found to be superior in terms of current switching ratio, average subthreshold swing and turn-on voltage. The probable fabrication process flow is also discussed for the proposed device and based on the proper benchmarking, it is revealed that improvement in the parameters like low-output voltage, peak overshoot and rise time defining the switching characteristics of an inverter makes the proposed device more suitable for digital circuit-based applications.

Physical Vapor Transport Growth of Antiferromagnetic CrCl3 Flakes Down to Monolayer Thickness.

The van der Waals magnets CrX3 (X=I, Br, and Cl) exhibit highly tunable magnetic properties and are promising candidates for developing novel two-dimensional (2D) spintronic devices such as magnetic tunnel junctions and spin tunneling transistors. Previous studies of the antiferromagnetic CrCl3 have mainly focused on mechanically exfoliated samples. Controlled synthesis of high quality atomically thin flakes is critical for their technological implementation but has not been achieved to date. This work reports the growth of large CrCl3 flakes down to monolayer thickness via the physical vapor transport technique. Both isolated flakes with well-defined facets and long stripe samples with the trilayer portion exceeding 60µm have been obtained. High-resolution transmission electron microscopy studies show that the CrCl3 flakes are single crystalline in the monoclinic structure, consistent with the Raman results. The room temperature stability of the CrCl3 flakes decreases with decreasing thickness. The tunneling magnetoresistance of graphite/CrCl3 /graphite tunnel junctions confirms that few-layer CrCl3 possesses in-plane magnetic anisotropy and Néel temperature of 17K. This study paves the path for developing CrCl3 -based scalable 2D spintronic applications.

Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor

Tunnel field effect transistors (TFETs) offer advantage of robustness against short channel effects. However, reliability issues caused by interface trap charges (ITCs) generated during the fabrication in TFET is a major concern. Thus, in this manuscript, device reliability of proposed lateral dual gate oxide (DGO) bilateral tunnelling-based Tunnel FET (BT-TFET) has been examined for the first time. In this device, gate dielectric employs dual oxide, which enhances capacitive coupling between the gate and dielectric, thus, boosting various performance parameters of the device. Observation has been made that the proposed DGO BT-TFET exhibits enhanced ION/IOFF ratio of around 1012 and reduced subthreshold swing of 7.17 mV/decade against ION/IOFF ratio of around 107 and subthreshold swing of 17.82 mV/decade exhibited by the conventional device. Device reliability of the proposed device has been examined through a comparison of the effects of positive and negative trap charges on the DC, Analogue/RF attributes, for instance electric field, transfer characteristics, cut-off frequency (fT), etc. of the proposed DGO BT-TFET and traditional single gate oxide (SGO) BT-TFET. The study reveals that positive (negative) ITCs increase (decrease) the ON-state current, fT of DGO BT-TFET and SGO BT-TFET by 37.82 % (29.62 %), 25.07 % (28 %) and 538.57 % (99.99 %), 430.76 % (96.5 %) respectively. Besides, linearity distortion parameters for instance second order voltage intercept point (VIP2), third order transconductance coefficients etc. and transient analysis have also been studied and compared for both the devices. It turns out that positive (negative) interface traps enhance (reduce) VIP2 of DGO BT-TFET and SGO BT-TFET by 4.2 % (0.81 %) and 76.3 % (81.3 %), respectively. Thus, indicating that DGO BT-TFET has enhanced resistance in terms of performance variation when compared with SGO BT-TFET for various ITCs.