Contact Trench Research Articles

Al-Si contact formation involving back surface field and voids of PERC

Local Al–Si contacts are a vital part of passivated emitter and rear cell (PERC) solar cells. They are generally fabricated using laser ablation to open the passivation dielectric layers, which is followed by Al paste printing and high-temperature alloying. However, the alloying process of Al–Si contacts and the formation mechanism of voids remain unclear in parts. In this study, based on the Al–Si binary phase diagram, we revealed the formation path associated with the back surface field (BSF) of the Al–Si alloying process and elucidated the formation mechanism of voids for dashed shape local contact openings. Also, a calculation model is proposed to determine and verify the Si concentration at the peak temperature. During peak-temperature firing, an equilibrium is established between the dissolution and diffusion of Si; subsequently, Si in the melt reaches its saturation concentration and laterally diffuses into the Al layer, thereby causing the net outflow of Si with the contact trench expansion and forming partial voids. During cooling, supersaturated Si precipitates to form BSF, while the degree of precipitated Si limits the thickness and forms the hypereutectic alloy. After the BSF formation, the melt was redistributed along the contact trench, resulting in partial voids turning into complete voids and fully filled contacts. This study also provides a new approach for regulating and optimizing Al–Si contacts. • The formation path of the back surface field of Al Si contact is revealed from the phase diagram. • Silicon saturated at peak temperature and BSF thickness is limited by the degree of silicon precipitation. • The contact of Hypereutectic component Al Si will affect the electrical properties. • The formation of voids is related to the lateral diffusion of silicon and the redistribution of melt. • The redistribution of melt transforms partial voids into complete voids.

Novel anode Schottky trench contact controlled SOI LIGBT with low loss and snapback-free

Novel anode Schottky trench contact controlled SOI LIGBT with low loss and snapback-free

Superjunction MOSFET with a trench contact on partly relatively lightly doped P-pillar for excellent reverse recovery

A superjunction metal-oxide-semiconductor field-effect transistor (SJ-MOSFET) with a trench contact on partly relatively lightly doped p-pillar is proposed and investigated by TCAD simulations. At reverse conduction state, since electrons in the n-pillar can be easily collected by the trench contact, the hole injection efficiency of the body diode can be lowered to reduce the reverse recovery charge (Q rr). Besides, the partly relatively lightly doped p-pillar increases the resistance of the hole extraction path so as to increase softness. Simulation results show that the proposed SJ-MOSFET can obtain a 46% lower Q rr than the conventional SJ-MOSFET and significantly suppress reverse recovery oscillations.

Design and Optimisation of Schottky Contact Integration in a 4H-SiC Trench MOSFET

Planar Schottky contact and various trench Schottky contacts have been integrated into the edge termination region of a 4H-SiC trench metal-oxide-semiconductor field-effect-transistor (MOSFET). The forward and reverse characteristics of various design splits have been benchmarked to determine the optimum method of the Schottky contact integration. As a result, the trench Schottky diode with Schottky metal contact in both the planar surface and the trench sidewall surface has been able to offer the best performance.

Effect of cell size reduction on the threshold voltage of UMOSFETs

UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage increase appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the increase in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the increase in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the increase in Vth. We established an analytical model for the increase in Vth. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a increase in Vth, but also it is difficult to control Vth using the conventional channel implantation method.

Impact of Si(100) doping methods on TiSi2 formation in vertical and horizontal FET structure areas with increasing aspect ratio

Due to the increasing complexity of FET structures and the preferred high trench aspect ratios, demanding process challenges exist, not only in the structuring of the contact trenches, but also in the uniform doping of the diffusion area. Previous investigations have mainly analyzed the doping of horizontal contact areas. For this reason, this paper demonstrates how vertical and horizontal contact areas can be doped through the side wall at the same time. For this purpose, relationships between structural geometry and doping methods are studied in order to structure a multitude of contact trenches next to each other in a functional way, which can realize source and drain trenches. By means of an ion implanted test structure, high doping concentrations of up to 1019 cm−3 could be achieved at a depth of approx. 250 nm below the 2.5 μm deep contact trench bottom. The concentration which can be obtained by PSG diffusion decreases rapidly with increasing Si depth. For the first time, it is shown that the dopant particle concentration of ion implantation increases with trench height and proximity to the trench side wall. Accordingly, the electrical conductivity is also higher and the SR value lower. A positive effect of the near-surface doping concentrations on the subsequent C49-TiSi2 formation could be demonstrated, which enables uniform film growth. In contrast, dopant deposition generates asymmetric dopant concentrations and prevents uniform silicide formation as the aspect ratio increases, thus causing higher diffusion area resistances.

Nearly Epitaxial Low-Resistive Co Germanide Formed by Atomic Layer Deposited Cobalt and Laser Thermal Annealing

With ALD-Co on n+ -Ge (ND of $2\times {10}^{{19}}\text {cm}^{\text {-3}}$ ) as the platform, annealing schemes including rapid thermal annealing (RTA) and laser thermal annealing (LTA) were employed to study its impact on the characteristics of CoGe2. CoGe2 formed by LTA shows no agglomeration and a low $\rho _{\text {c}}$ of $1.3\times {10}^{\text {-8}} \Omega $ -cm2 which is reduced by 54 % as compared to the counterpart RTA. In addition, a uniform and atomically smooth CoGe2 with nearly epitaxial crystal structure is also achieved by LTA. Furthermore, LTA-formed CoGe2 does not require any barrier layer during formation which is in stark difference to other germanides and would greatly improve line resistance of the ever scaled contact trench. The promising results mainly stem from the low thermal budget with significant thermal gradient/shallow heat distribution of LTA that effectively limits excess surface Co diffusion and grooving effect, proving the high contact performance enabler beyond 5 nm node.

Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology

We report record low $8.4\times 10^{-10}~\Omega $ -cm2 n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

3.3 kV-Class 4H-SiC UMOSFET by Double-Trench with Tilt Angle Ion Implantation

A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability

A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. 3-D self-consistent electrothermal simulations, tuned with experimentally measured electrical characteristics, were used to understand the nature of self-heating in FinFETs and calibrate the proposed model. The accuracy of the model has been demonstrated for a wide range of multifin devices by comparing it against finite element simulations. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures, which are critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability. The transient model has been used to estimate the thermal time constants of these devices and predict the sensitivity of power-to-failure to various device parameters, for both long and short pulse ESD situations. Suitable modifications to the model are also proposed for evaluating the thermal characteristics of production level FinFET (or Tri-gate FET) structures involving metal-gates, body-tied bulk FinFETs, and trench contacts.

A Leakage Current Induced by Barrier Metal Formation in Power MOSFETs with Trench Contact Structure

One of important parameter of Power MOSFET is ON resistance (RON) to minimize power loss in power system. To minimize RON, need high cell density process because channel resistance has occupied high proportional for total RON in low voltage Power MOSFET. Trench contact structure is suitable for high density device with narrow contact width. However in this structure case, designer should consider silicide formation due to high aspect ratio profile to prevent high leakage current. In this paper, present optimized Ti/TiN thickness formation to minimize leakage current between Drain and Source. Basically it shows good leakage performance that all removed Ti/TiN layer on the top of ILD by additional etchback or CMP process. And another finding from our study, optimized Ti/TiN formation also shows comparable leakage current with it. Unreacted Ti(+) ion is main contributed factor for high leakage current at P-channel device and higher wafer stress due to thicker TiN layer is another factor.

Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures

In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations.

Infrared spectroscopic ellipsometry applied to the characterization of nano-structures of silicon IC manufacturing

A new automated 300-mm metrology tool using infrared spectroscopic ellipsometry is presented. After a description of the specifications of the instrument with special attention on the spot size, the instrument specifications are described and different applications of the technique related to the IC technology are presented. We show in particular that physical and chemical information on new low- k dielectric materials can be obtained independently. Depth information can also be deduced in a non-destructive way for contact trenches in dielectric layers.

High-density trench gate DMOSFETs with trench contact structure

A novel process technique for fabricating trench gate DMOSFETs using the two-step trench technique and trench contact structure is realised to obtain higher cell density and lower on-resistance. Using this process technique, a remarkably increased trench gate DMOSFET with a cell pitch of 1.6 µm and a channel density of 130 Mcell/in2 are obtained. The fabricated device has a low specific on-resistance of 0.28 mΩ · cm2 with a blocking voltage of 43 V, which is about 23 % lower than that of the device fabricated by the previous method.

A New Dual-Channel Emitter Switched Thyristor (DC-EST) Employing a Self-Aligned Trenched Contact

A new Dual-Channel Emitter Switched Thyristor (DC-EST), which suppresses the inherent parasitic thyristor operation effectively by employing a self-aligned trench contact, has been proposed and verified by numerical device simulations. Simulation results show that the maximum controllable current density of the proposed DC-EST is about three times larger than that of the conventional DC-EST because the self-aligned trench contact reduces the resistance under the n+ cathode. It is noted that the forward voltage drop of the proposed DC-EST is lower than that of the conventional one by 0.2 V by reduced cell pitch.

A high-performance self-aligned UMOSFET with a vertical trench contact structure

We compare the electrical characteristics of a UMOSFET having a trench contact (TC-UMOS) for the source and the body regions with those of the conventional surface contact UMOSFET (SC-UMOS). For SC-UMOS, there exists an optimum cell pitch which gives the lowest on-resistance. Reducing the cell pitch beyond that point results in increased on-resistance because the source contact resistance increases as the cell pitch is further reduced. On the contrary, for TC-UMOS, the on-resistance decreases as the cell pitch is reduced because the source contact resistance does not change, These results show that TC-UMOS is more effective than SC-UMOS for reducing the on-resistance by scaling down of the cell pitch. The minimum specific on-resistance of TC-UMOS is 0.43 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the critical avalanche current of TC-UMOS is enhanced significantly compared with that of SC-UMOS because the base resistance of the parasitic npn-bipolar transistor of TC-UMOS is lower than that of SC-UMOS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Lithography for patterning trench contacts

Lithography processes suitable for the patterning of buried trench contacts were tested for two different stacked capacitor cell concepts and evaluated with respect to process latitudes.

Ultralow specific on resistance UMOSFET with trench contacts for source and body regions realised by selfaligned process

An ultralow on resistance power UMOSFET having a refined contact structure has been fabricated by a selfaligned process. The most important feature of this UMOSFET is its great increment of channel width per unit area, which leads to a noticeable reduction in the on resistance. A 50V UMOSFET with a specific on resistance of 0.58mΩcm2 has been achieved despite employing a relatively thick (520μm) substrate with a resistivity of 8mΩcm.