Tree Multiplier Research Articles

Modified low power Wallace Tree multiplier using higher order compressors

ABSTRACTIn recent trend, power management has become critical concern for all portable applications. High-power dissipation rises temperature profile of the chip and affects the performance of the design. Many techniques at different levels of design process have been recommended to reduce power dissipation. Multiplier is one of the major sources of power dissipation in application systems such as digital signal processor, microprocessor and application-specific integrated circuits. Designing multiplier with low-power, high-speed and minimal-layout structure is of prime importance. In this paper, we propose an 8 × 8 hybrid Wallace tree multiplier. The partial product reduction is done by higher order compressors such as 3:2, 4:2, 5:2, 6:2, 7:2 and 8:2. These compressors are designed and implemented using various adders such as 8T, 10T, 14T and Gate Diffusion Input. The design is simulated and implemented by DSCH2 and MICROWIND tool. The simulation results reveal that the proposed multiplier achieves about 55% power saving compared to conventional tree multiplier structures. A large amount of reduction in wiring head is attained for the proposed multiplier.

Low Power, High Speed and Area Efficient Binary Count Multiplier

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Performance improvement in tree multiplier using full swing GDI logic based CLA adder

Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.

Performance improvement in tree multiplier using full swing GDI logic based CLA adder

Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.

Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit

In this work we present a new 64-bit floating point Fused Multiply Add (FMA) unit that can perform both binary and decimal addition, multiplication, and fused-multiply-add operations. The presented FMA has 6 percent less delay than the fastest stand-alone decimal unit and 23 percent less area than both binary and decimal units together. These results were achieved by the use of: 1) column by column reduction to reduce the partial products in the multiplier tree, 2) a new leading zeros detector that produces its output in base-3 to simplify the normalization shifting in the binary datapath, 3) the use of a redundant adder to perform the final addition, 4) using a new rounding-while-redundant technique to hide the rounding delay and remove it from the critical path, and 5) using a new simple conversion technique from redundant to binary/decimal.

An optimized embedded adder for digital signal processing applications

In this paper, an embedded logic full adder (PRO-FA) circuit in transistor level is proposed that reduces logic complexity, consumes low power, and is low area. The design is implemented for 1 bit and then is further extended to 64 bits. The area obtained for 1-bit PRO-FA is 2.85 $ {\mu }{m}^{{2}}$ and is built using only 13 transistors. The PDP of the proposed adder is ${459.4\times }{{10}}^{{-18}} Ws $ and ADP is 128.25 $\mu {m}^{{2}}ps $ and is compared with the earlier reported designs. Furthermore, a 16-, 32-, 64-bit both linear and square-root carry select adder/subtractor (CSLAS) structure is proposed. Realistic testing in terms of power and delay is performed for the proposed logic by implementing it on 8 $\times $ 8 modified Booth, array, and Wallace tree multiplier architectures. The efficiency of the proposed circuits in DSP architecture like 4-tap FIR filter is demonstrated. Overall delay for CSLAS is reduced to 70% when compared to the conventional one. The implementations are done using the Cadence Virtuoso tool with TSMC 28 nm LP CMOS technology and are found to have power savings of up to 76%. The present proposed architectures offer significant improvement in terms of power and speed in comparison to other reported architectures.

High Speed Area Efficient 32 Bit Wallace Tree Multiplier

A 32 bit high speed area efficient Wallace tree multiplier is designed using verilog HDL and implemented in FPGA. The circuit is designed using carry save adder architecture and finally with one look ahead carry adder. The design is an improved version of tree based Wallace tree multiplier architecture. This paper aims at high speed multiplication and an area efficient 32 bit Wallace tree multiplier. The entire design is coded in Verilog HDL, simulated with Modelsim and synthesized using Xilinx FPGA device. The result shows that the proposed architecture takes very less time for computing the multiplication of two 32 bit numbers. In terms of area also, the proposed multiplier is much efficient than the existing methods. The frequency of operation of the circuit is 200 MHz. General Terms Algorithm, Verilog code, Multipliers

A Low Power Multiplier using a 24-Transistor Latch Adder

Background: Multiplication forms one of the most power hungry operations in a digital system. It is used extensively in the digital signal processing applications and in any general purpose processors. Hence, the efficient hardware realization of the multiplier is crucial in ensuring that the processors operate within the power limits and without getting overheated. Method: In order to make the multipliers more power efficient, ways have been found to curtail the spurious glitching in the internal nodes of the multiplier. Latch adder with the delay lines is used in the multiplier to equalize the delay of the partial products. Findings: In this paper, a novel 24 transistor Latch Adder (LA) is proposed. It is validated using the Wallace tree multiplier as a bench marking circuit. Wallace tree multiplier is implemented using the proposed latch adder and delay lines in the internal nodes. Comparison is made with the multipliers constructed using various full adder configurations available in the literature. Conclusion: It is proved that the proposed multiplier circuit achieves the power reduction of 20% compared to the multiplier using 16T full adder. The multiplier is simulated using the industry standard Cadence® Virtuoso tool in 180nm technology library files and the simulation results confirm the low power operation of the multiplier.

FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase

Multipliers are frequently used to reduce the delay of array multipliers. The objective of tree multipliers is to utilize the concept of carry save adders in reducing the partial product. Two well known tree multipliers Wallace and Dadda uses full adders and half adders for the aforesaid purpose. This paper implements a multiplier which will perform reduction of partial products using 4 bit Carry Lookahead Adders primarily instead of Full adders. This will result in fewer reduction stages as Full adders reduces 3 partial products bits to 2 giving a 1.5 to 1 ratio whereas 4 bit CLA will reduce 9 partial products bits to 5 giving 1.8 to 1 ratio. Xilinx Spartan 3E FPGA board is used for implementation of structural verilog code for the multiplier design. KeywordsMultiplier, Wallace, Dadda, Carry Lookahead Adders.

Design and Implementation of Booth Multiplier using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. Keyword: Approximate computing, low power, mirror adder. Booths multiplier, Wallace tree multiplier I. INTRODUCTION Digital signal processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. Most of these DSP blocks implement image and video processing algorithms, where the ultimate output is either an image or a video for human consumption. Human beings have limited perceptual abilities when interpreting an image or a video. This allows the outputs of these algorithms to be numerically approximate rather than accurate. This relaxation on numerical exactness provides some freedom to carry out imprecise or approximate computation. We can use this freedom to come up with low-power designs at different levels of design abstraction, namely, logic, architecture, and algorithm. The paradigm of approximate computing is specific to select hardware implementations of DSP blocks. It is shown in (1) that an embedded reduced instruction set computing processor consumes 70% of the energy in supplying data and instructions, and 6% of the energy while performing arithmetic only. Therefore, using approximate arithmetic in such a scenario will not provide much energy benefit when considering the complete processor. Programmable processors are designed for general-purpose applications with no application-specific specialization. Therefore, there may not be many applications that will be able to tolerate errors due to approximate computing. This also makes general-purpose processors not suited for using approximate building blocks. This issue has already been discussed in (13). Therefore, in this paper, we consider application-specific integrated circuit implementations of error-resilient applications like image and video compression.

A high-speed multiplexer-based fine-grain pipelined architecture for digital fuzzy logic controllers

Design and implementation of a high-speed multiplexer-based fine-grain pipelined architecture for a general digital fuzzy logic controller has been presented. All the operators have been designed at gate level. For the multiplication, a multiplexer-based modified Wallace tree multiplier has been designed, and for the division and addition multiplexer-based non-restoring parallel divider and multiplexer-based Manchester adder have been used, respectively. To further increase the processing speed, fine-grain pipelining technique has been employed. By using this technique, the critical path of the circuit is broken into finer pieces. Based on the proposed architecture, and by using Quartus II 9.1, a sample two-input, one-output digital fuzzy logic controller with eight rules has been successfully synthesised and implemented on Stratix II field programmable gate array. Simulations were carried out using DSP Builder in the MATLAB/Simulink tool at a maximum clock rate of 301.84 MHz.

Design of Digital FIR Filter Based on MCMAT for 12 bit ALU using DADDA & WALLACE Tree Multiplier

Over a period of time, there are different types of multipliers used to minimize cost of constructive parameters in digital FIR filter design in different forms. In these multipliers truncated multiplier design play’s an essential role. Due to multiple adders and delay elements the circuit in transpose form occupies more area and consumes power. In the proposed method effectiveness in different parameters are achieved with low cost, high speed and effective results are done by faithfully rounded truncated multipliers with operations of carry save adder. Direct form of FIR filter utilizes based on MCMAT for multiplication and accumulation operations; it will reduce the area by decreasing the number of different components like structural adders and registers. By using MCMAT operation in the digital FIR filters, optimal results can be obtained in terms of power and area specifications. The proposed 12 bit Arithmetic and Logic Unit is designed along with MCMAT based digital FIR filter for reducing area and increasing speed in real time applications.

An Efficient Hardware-Based Higher Radix Floating Point MAC Design

This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance computation with greater accuracy. In general, digital signals are represented as a sequence of signed/unsigned fixed/floating point numbers. The final result of a MAC operation can be computed by feeding the mantissa of the previous MAC result as one of the partial products to a Wallace tree multiplier or Braun multiplier. Thus, the separate accumulation circuit can be avoided by keeping the circuit depth still within the bounds of the Wallace tree multiplier, namely O ( log 2 n ), or Braun multiplier, namely O ( n ). In this article, three kinds of floating point MACs are proposed. The experimental results show 48.54% of improvement in worst path delay achieved by the proposed floating point MAC using a radix-2 Wallace structure compared with a conventional floating point MAC without a pipeline using a 45nm technology library. The same proposed design gives 39.92% of improvement in worst path delay without a pipeline using a radix-4 Braun structure as compared with a conventional design. In this article, a radix-32 Q 32.32 -format-based floating point MAC is proposed using a Wallace tree/Braun multiplier. Also this article discusses the msb prediction problem and its solution in floating point arithmetic that is not available in modern fused multiply-add designs. The performance results show comparisons between the proposed floating point MAC with various floating point MAC designs for radix-2,-4,-8, and -16. The proposed design has lesser depth than a conventional floating point MAC as well as a lower area requirement than other ways of floating point MAC implementation, both with/without a pipeline.

English

Audio restoration is effectively achieved by using low complexity algorithm called AMP. This algorithm has fast convergence and has lower computation intensity making it suitable for audio recovery problems. This paper focuses on restoring an audio signal by using VLSI architecture called AMP-M that implements AMP algorithm. This architecture employs MAC unit with fixed bit Wallace tree multiplier, FFT-MUX and various memory units (RAM) for audio restoration. VLSI and FPGA implementation results shows that reduced area, high throughput, low power is achieved making it suitable for real time audio recovery problems. Prominent examples are Magnetic Resonance Imaging (MRI), Radar and Wireless Communications.

AREA EFFICIENT DISTRIBUTED ARITHMETIC DISCRETE COSINE TRANSFORM USING MODIFIED WALLACE TREE MULTIPLIER

In this study by using the modified Wallace tree multiplier, an error compensated adder tree is constructed in order to round off truncation errors and to obtain high through put discrete cosine transform design. Peak Signal to Noise Ratio (PSNR) is met efficiently since modified Wallace Tree method is an efficient, hardware implementable digital circuit that multiplies two integers resulting an output with reduced delays and errors. Nearly 6% of delays and around 1% of gate counts are reduced. The number of look up tables consumed is 2% lesser than that of the previous multipliers. Thus an area efficient discrete cosine transform is built to achieve high throughput with minimum gate counts and delays for the required Peak Signal to Noise Ratio when compared to the existing DCT’s.

Performance Analysis of Different Multipliers using Square Root Carry Select Adders

A high-speed and energy-efficient multiplier is always required in electronics industry particularly in digital signal processing, arithmetic units in microprocessor and image processing. Multiplier is a significant element which contributes to the total power utilization of the system. By comparing different types of adders it is found that the ripple carry adder has a smaller area with lesser speed performance, in contrast to which carry select adders have high speed but posses a larger area. In the existing models of the multipliers, the regular square root carry select adder and modified square root carry select adder using Binary to Excess-1 logic are designed and implemented on both Array and Wallace tree multipliers respectively. In the proposed work a proficient square root carry select adder is designed using common Boolean logic and is implemented on both Array and Wallace tree multipliers respectively. A well-organized Verilog code has been written and successfully synthesized and simulated using Xilinx ISE 14.2. The simulation results gives the performance of Array and Wallace tree multipliers using proposed square root carry select adder is excellent compared with other structures of square root carry select adders.

Carry-based reduction parallel counter design

Parallel counters are one of the important components to construct high performance DSP units including column compression multipliers (i.e. tree multipliers). As the multiplier size increases, designing optimised wider counters is critical for its performance, which is the motive of this study. This article proposes a novel approach to design (2 n −1, n) parallel counter using a reduction stage and a single (2 n −1 −1, n − 1) parallel counter. An algorithm to construct the reduction stage for any counter size is presented. The designs of parallel counter examples using the proposed algorithm are discussed. Finally, the proposed design performance metrics (in terms of delay, power and energy-delay-product) are compared with the conventional parallel counter designs. The proposed designs achieve 13% average speed up, 10% power reduction and 32% improvement in energy-delay-product compared with conventional counters.

Models for characterizing noise based PCMOS circuits

Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in the early stage of research, PCMOS has shown potential to drastically reduce energy consumption at a cost of increased errors. Recently, a methodology has been proposed which could predict the error rates of cascade structures of blocks in PCMOS. This methodology requires error rates of unique blocks to predict the error rates of multiblock cascade structures composed of these unique blocks. In this article we present a new model for characterization of probabilistic circuits/blocks and present a procedure to find and characterize unique circuits/blocks. Unlike prior approaches, our new model distinguishes distinct filtering effects per output, thereby improving prediction accuracy by an average of 95% over the prior art by Palem and coauthors. Furthermore, we show two models where our new model with three stages is 18% more accurate, on average, than our simpler two-stage model. We apply our proposed models to Ripple Carry Adders and Wallace Tree Multipliers and show that using our models, the methodology of cascade structures can predict error rates of PCMOS circuits with reasonable accuracy (within 9%) in PCMOS for uniform voltages as well as multiple voltages. Finally, our approach takes seconds of simulation time whereas using HSPICE would take days of simulation time.

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Transfer Torque-Magnetic Tunneling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated and compared by implementing a 16-bit carry look-ahead adder and a 32-bit Wallace tree multiplier in STLA and FPGA.

Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors

In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the counters to deal with temperature effect, reliability improvement, and operating speed with multipliers. Simulation results with the proposed phase-modulated (7:3) counter show that it is able to work at room temperature with a delay of 1.5 ns, power dissipation of 4.1 μW at frequency of 100 MHz, and maximum tolerable background charges of up to 0.2e with the worst-case delay of 3 ns.