This paper presents an 8-element phased-array heterodyne transceiver (TRX) chip for 60-GHz wireless applications. The chip integrates transmit/receive (T/R) elements, bi-directional variable-gain driving amplifiers (BI-VGDAs), up/down mixing chains, and the local oscillator (LO) chain. To support the time division duplexing (TDD) operation and increase output power, a low-loss compact on-chip antenna T/R switch is introduced by embedding it in the power amplifier (PA) power combiner, thereby achieving a high transmitter (TX) output power and low receiver (RX) noise figure (NF), respectively. Fabricated in a 65-nm CMOS process, the proposed phased array TRX chip occupies an area of 5.1 mm × 2.5 mm. With measurements, the TX path provides a 32-dB maximum conversion gain, an 11.3-dBm OP1dB, and a 16-dBm Psat, respectively. The RX path achieves a peak gain of 24 dB and an NF of 6.5–9 dB across 57–66 GHz. With the 16-QAM modulation, a 7.04 Gb/s data rate is demonstrated.
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