Transistor Logic Research Articles

(Invited) Investigation of Phosphorene in Electrochemical Energy Storage Devices

Among the family of atomically thin two-dimensional (2D) materials, phosphorene (a monolayer of black phosphorus) has special significance since it offers a direct band gap that lies in-between the zero gap graphene and various large band gap 2D transitional metal dichalcogenides. Phosphorene is an atomically thin sheet in which each phosphorus atom bonds with three neighboring atoms forming a puckered honeycomb structure. So far the research community has mainly focused on the electronic and opto-electronic applications of phosphorene such as logic transistors and photo-detectors. The exploration of this unique material in electrochemical energy storage is still very much in its infancy. In my talk, I will show that incorporation of few-layer nanosheets of phosphorene into a porous carbon nanofiber network (cathode matrix) can significantly improve the cycle life of Lithium-Sulfur (Li-S) batteries. After 500 continuous cycles of charge-discharge, the specific capacity of the Li-S battery with phosphorene is retained above 660 mAh g−1 with only ~0.053% capacity decay per cycle, much better than the baseline battery (without phosphorene) which shows ~0.25% capacity fade per cycle in only 200 cycles under the same test condition. First-principles density functional theory calculations indicate that this improvement is related to phosphorene’s ability to immobilize lithium polysulfides. The binding energy of various lithium polysulfides to phosphorene ranges from 1-2.5 eV, which is significantly greater than a carbon hexatom network (~0.5 eV). Our results also indicate that the presence of phosphorene lowers the polarization, accelerates the redox reaction and improves sulfur utilization in the battery. Such work indicates the promise of phosphorene and will give further impetus to the research community to explore the fundamental science and applications of phosphorene in the context of electrochemical energy storage.

Design of high speed and low power 4-bit comparator using FGMOS

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13μm technology with the supply voltage of 1V.

Manipulating Surface States of III-V Nanowires with Uniaxial Stress.

III-V compound semiconductors are indispensable materials for today's high-end electronic and optoelectronic devices and are being explored for next-generation transistor logic and quantum technologies. III-V surfaces and interfaces play the leading role in determining device performance, and therefore, methods to control their electronic properties have been developed. Typically, surface passivation studies demonstrated how to limit the density of surface states. Strain has been widely used to improve the electronic transport properties and optoelectronic properties of III-Vs, but the potential of this technology to modify the surface properties still remains to be explored. Here we show that uniaxial stress induces a shift in the energy of the surface states of III-V nanowires, modifying their electronic properties. We demonstrate this phenomenon by modulating the conductivity of InAs nanowires over 4 orders of magnitude with axial strain ranging between -2.5% in compression and 2.1% in tension. The band bending at the surface of the nanostructure is modified from accumulation to depletion reversibly and reproducibly. We provide evidence of this physical effect using a combination of electrical transport measurement, Raman spectroscopy, band-structure modeling, and technology computer aided design (TCAD) simulations. With this methodology, the deformation potentials for the surface states are quantified. These results reveal that strain technology can be used to shift surface states away from energy ranges in which device performance is negatively affected and represent a novel route to engineer the electronic properties of III-V devices.

Transformation of amorphous to crystallized carbon

Graphene has attracted much attention in materials science and electronics because of its high conductivity, strong mechanical strength, excellent flexible properties, etc. The favored fabrication method of graphene is using methane by chemical vapor deposition. Through this method high quality and large-scale monolayer graphene has been prepared. However, this graphene is not suitable for use in preparation of logical transistor devices, owing to the insufficient band gap. On the other hand, graphene nanoribbon has a finite band gap and a N-doped graphene monolayer shows a low on/off current ratio. Therefore, it is necessary to develop fabrication techniques for making graphene that is appropriate for logic devices. This paper introduces an easy fabrication method that does not need a methane source, where a solid phase source transformation to crystallize graphene is carried out on polycrystalline Copper foil, and a N-doped graphene layer is produced. Bilayer graphene is found to be achieved at most hydrogen flow rates.

Feeding Experimentation Device (FED): Construction and Validation of an Open-source Device for Measuring Food Intake in Rodents.

Food intake measurements are essential for many research studies. Here, we provide a detailed description of a novel solution for measuring food intake in mice: the Feeding Experimentation Device (FED). FED is an open-source system that was designed to facilitate flexibility in food intake studies. Due to its compact and battery powered design, FED can be placed within standard home cages or other experimental equipment. Food intake measurements can also be synchronized with other equipment in real-time via FED's transistor-transistor logic (TTL) digital output, or in post-acquisition processing as FED timestamps every event with a real-time clock. When in use, a food pellet sits within FED's food well where it is monitored via an infrared beam. When the pellet is removed by the mouse, FED logs the timestamp onto its internal secure digital (SD) card and dispenses another pellet. FED can run for up to 5 days before it is necessary to charge the battery and refill the pellet hopper, minimizing human interference in data collection. Assembly of FED requires minimal engineering background, and off-the-shelf materials and electronics were prioritized in its construction. We also provide scripts for analysis of food intake and meal patterns. Finally, FED is open-source and all design and construction files are online, to facilitate modifications and improvements by other researchers.

Static and Dynamic Magnetization Investigation in Permalloy Electrodeposited onto High Resistive N-Type Silicon Substrates

The present study reports on the development of permalloy thin films obtained by electrodeposition onto low-doped n-type silicon substrates. While changing from non-percolated clusters into percolated thin films upon increasing the electrodeposition time, the static and dynamic magnetic properties of the as-obtained structures were investigated. We found the experimental magnetic results to be in very good agreement with the simulations performed by solving the Landau-Lifshitz for the dynamics of the magnetic moment. For short electrodeposition times we found the static and dynamic magnetization behavior of the as-formed nanoclusters evidencing vortex magnetization with random chirality and polarization, which is explained in terms of dipolar interaction minimization. Indeed, it is herein emphasized that recent applications of ferromagnetic materials in silicon-based spintronic devices, such as logic and bipolar magnetic transistors and magnetic memories, have revived the possible utilization of low cost and simple electrodeposition techniques for the development of these upcoming hetero-nanostructured devices.

Effects of impedance mismatch and coaxial cable length on absolute gravimeters

The systematic effects of absolute gravimeters have to be investigated to fully utilize their capabilities in metrology and geosciences. In Křen et al (2016 Metrologia 53 27–40) we found that for an FG5 gravimeter, even a few meter long coaxial cable used for transmission of fringe signal causes systematic features in residuals and errors at the level of 1–2 µGal. In this paper, we present experimental results and appropriate models to explain the effects that were found to be caused by impedance mismatches of electronic components and dispersion effects in coaxial cables of gravimeters. The experimental results have been obtained for analogue and transistor–transistor logic (TTL) compatible signals in the FG5-215 gravimeter and for a TTL signal in the FG5X-251 gravimeter. We found that dispersion and impedance mismatch effects are similar for both gravimeters. Furthermore, we describe a model of the dispersion that allows an evaluation of the effect/correction for a given range of the free-fall and thus it is also applicable to other gravimeters. The effect of impedance mismatch for the analogue fringe signal is modelled as an effect of the reflected electronic signal on the evaluation of zero-crossings. The applicability of this model for TTL signal is also discussed.

Systematic Investigation of Self-Heating Effect on CMOS Logic Transistors From 20 to 5 nm Technology Nodes by Experimental Thermoelectric Measurements and Finite Element Modeling

The characteristics of thermal conductivity(k) with different operated temperatures (T), material thicknesses (t), and impurity concentrations (N) are studied by thermoelectric measurements and developed simulation model for the study of self-heating effect. With the input of these module-level material properties in our developed finite-element model, the self-heating effect on the CMOS logic transistors from 20to 5-nm technology nodes are investigated systematically and accurately. The maximum chip temperature in the 14/16-nm technology node Si FinFET device is ~170 °C. On the other hand, the higher operated temperature is also observed in high mobility material devices such as Ge and III-V (InAs) FinFETs due to their poor material properties of k-value. It indicates that these high mobility materials are hard to be used in the next generation scaled technology node devices, unless these devices can be operated at the ultralow voltage bias (<;0.5 V for InAs and <;0.8 V for Ge) from the self-heating effect point of view.

An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead.

An integrated device with high performance multi-function generators and time-to-digital convertors.

A highly integrated, high performance, and re-configurable device, which is designed for the Nitrogen-Vacancy (N-V) center based quantum applications, is reported. The digital compartment of the device is fully implemented in a Field-Programmable-Gate-Array (FPGA). The digital compartment is designed to manage the multi-function digital waveform generation and the time-to-digital convertors. The device provides two arbitrary-waveform-generator channels which operate at a 1 Gsps sampling rate with a maximum bandwidth of 500 MHz. There are twelve pulse channels integrated in the device with a 50 ps time resolution in both duration and delay. The pulse channels operate with the 3.3 V transistor-transistor logic. The FPGA-based time-to-digital convertor provides a 23-ps time measurement precision. A data accumulation module, which can record the input count rate and the distributions of the time measurement, is also available. A digital-to-analog convertor board is implemented as the analog compartment, which converts the digital waveforms to analog signals with 500 MHz lowpass filters. All the input and output channels of the device are equipped with 50 Ω SubMiniature version A termination. The hardware design is modularized thus it can be easily upgraded with compatible components. The device is suitable to be applied in the quantum technologies based on the N-V centers, as well as in other quantum solid state systems, such as quantum dots, phosphorus doped in silicon, and defect spins in silicon carbide.

Design and Analysis of Low Power High Speed Hybrid Logic 8-T Full Adder Circuit

Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.

Design of a Low Power and High Speed Comparator using MUX based Full Adder Cell for Mobile Communications

This paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate the threshold voltage loss problem which is commonly encountered in Pass Transistor Logic (PTL) design. The proposed design successfully embeds the buffering circuit in the full adder design which helps the cell to operate at lower supply voltage compared with the other related existing designs. It also enhances the speed of the cascaded operation significantly while maintaining the performance edge in energy consumption. In the proposed design, the transistor count is minimized. For performance comparison, the proposed MUX-6T comparator (1-bit) is compared with four existing full adders based comparators using BSIM4 model parameters. The simulations are performed for 65nm process models indicate that the proposed design has lowest energy consumption along with the performance edge in both speed and energy consumption. The variants namely area and power of the proposed comparator is also compared with the published author designs to validate its suitability for low power and high speed mobile communication applications.

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures 600 μs at 1.1 V and 85℃, enhancing by 87.5% over the conventional design approach.

An all-optical switch and third-order optical nonlinearity of 3,4-pyridinediamine

We investigated the third-order nonlinear optical properties of 3,4-pyridinediamine solution. The nonlinear measurements were taken by using single-beam Z-scan technique with cw laser at 473 nm. The effect of varying glucose concentration in a sample solution has been studied. The experimental results show that the nonlinear refractive index, n 2, and nonlinear absorption coefficient, β, are strongly dependent on the glucose concentration in a sample solution. The optical limiting properties are measured by a transmission technique. We find that the limiting threshold can be improved by a proper choice of glucose concentration in sample solution. A 3,4-pyridinediamine with 80 mmol glucose concentration showed a good switching property. This phenomenon was demonstrated by waveguiding a transistor–transistor logic modulated cw 473 nm laser beam as an excitation beam modulated at 10 Hz frequency collinearly with a continuous-wave SDL-635-100T laser beam of wavelength 653 nm through a quartz cuvette of thickness 1 mm. The results of pump–probe experiments show that the time of switch-on and switch-off of the 3,4-pyridinediamine was in μs for the pump intensity. The energy-dependent transmission studies also reveal better limiting property of the sample compound at nanosecond regime. Also, thermo-optic coefficients have been determined by thermal lens (TL) technique (−9.54 × 10−5 K−1) and it was found to be temperature dependent. This value was compared with result obtained by Z-scan calculations (−7.46 × 10−5 K−1). Thus, the nonlinear response of the material suggests that it has a potential application for high-sensitive photonic devices.

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic Complementary Inverters

We present a design approach to maintain a stable voltage transfer characteristic in inkjet-printed complementary organic thin-film transistor logic inverters via device sizing. We use transistor-level design to help achieve stable logic gates, so that performance is less dependent on processing conditions and materials properties that are difficult to control for inkjet-printed electronics. Despite bias-stress instability in the individual p- and n-type transistors, a stable inverter switching threshold is achieved by equalizing the magnitudes of positive and negative threshold voltage shifts. Following a typical sizing approach for complementary logic, a p- to n-transistor transconductance ratio of 0.25 places the inverter switching threshold near the center of the voltage supply range. However, we show through calculations and measured results that a ratio closer to 2.5 prevents rapid shift of the switching threshold, which is equally important for reliable inverter operation. Furthermore, we provide a design approach to size digital logic gates with arbitrary probability of output states.

Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit

The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32bit carry increment adder (CIA) circuit is designed by bit slice method. The CIA adder layout gives tremendous change compared to existing author results. The proposed circuit achieved better performance on power consumption, speed, throughput, and area. The 32-bit adder circuits are implemented in various types of 1-bit adder cells, such as Shannon, Mixed-Shannon and MCIT-7T. Furthermore, the 32-bit CIA adder layout is furtherly investigated for RLC interconnect parameter such as capacitive impedance, inductive impedance, power factor sin ϕ, tan ϕ for applying frequency. The 32bit adder circuit acts in a better way than existing circuits in terms of power dissipation, delay, throughput, latency, power factor, sin ϕ and tan ϕ.

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).

New Proposal for MCML Based Three-Input Logic Implementation

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

Vertically Integrated Nanowire-Based Unified Memory.

A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.