Off-state Transistor Research Articles

Radiation Hardness Study of L G = 20 nm FinFET and Nanowire SRAM Through TCAD Simulation

Radiation hardness of FinFET and stacked nanowire (NW) static random-access memory (SRAM), with ${L} _{\text {G}} =20$ nm, which corresponds to high-density 5 nm technology node, is studied and compared using 3-D technology computer-aided design (TCAD) full cell domain simulation. Single FinFET and NW of similar total height are created using process simulation. Two types of NWs are studied, namely, high-performance and low-power NW, which has the same OFF-state and ON-state current as the FinFET, respectively. Device simulations are performed using transport parameters calibrated in Monte Carlo simulations. Radiation hardness of both n-type and p-type devices are simulated by striking particles at various locations and directions when the transistors are at OFF-state. It is found that NW is more robust than FinFET in all strike locations and directions. Radiation strikes are then applied to the OFF-state transistors in the SRAM at the most vulnerable positions. The SRAMs of both devices are designed to have similar noise margins for a fair comparison. It is found that NW SRAM is much more robust and can sustain two to three times higher linear energy transfer (LET) than FinFET SRAM in the most striking locations. Therefore, from a radiation robustness perspective, NW SRAM is preferred.

An Analytical Model of Single-Event Transients in Double-Gate MOSFET for Circuit Simulation

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter.

In Situ Thermal Atomic Layer Etching for Sub-5 nm InGaAs Multigate MOSFETs.

Thermal atomic layer etching (ALE) was demonstrated on ternary III-V compound semiconductors. In particular, thermal ALE on InGaAs and InAlAs was achieved with sequential, self-limiting fluorination and ligand-exchange reactions using hydrogen fluoride (HF) as the fluorination reactant and dimethylaluminum chloride (DMAC) as the ligand-exchange reactant. Thermal ALE was investigated on planar surfaces and three-dimensional nanostructures. The measured radial etch rates on In0.53Ga0.47As and In0.52Al0.48As vertical nanowires (VNWs) at 300 °C were 0.24 and 0.62 Å/cycle, respectively. An optimized thermal ALE process did not increase the surface roughness after 200 cycles. The etching process also displayed selectivity and orientation dependence. This new thermal ALE process in combination with in situ atomic layer deposition (ALD) was used to fabricate InGaAs gate-all-around structures with minimum width down to 3 nm. The in situ ALE-ALD process produced a sharp vertical MOS interface. Finally, the merits of thermal ALE were demonstrated in the fabrication of n-channel InGaAs FinFETs with record ON-state and OFF-state transistor performance. On the basis of this transistor demonstration, thermal ALE shows great promise for high-volume device manufacturing.

A single event upset tolerant latch design

This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards. Two OFF-state transistors are added to those two internal pull-up paths, suppressing positive transient. Simulation and experimental data demonstrate that the proposed design has smaller cross section and higher upset threshold than the reference design.

An Asymmetric Nanoscale SOI MOSFET by Means of a P-N Structure as Virtual Hole’s Well at the Source Side

This paper suggests and investigates a p-n structure, which emulates as a MOSFET. In the proposed structure we utilize an L-shape contact with a proper work function over the source region of silicon on insulator MOSFET to convert the source region from p+ to n+. We check its performance by indicating the band diagram and electron and hole concentrations which acts as n-p-n transistor in OFF state. By employing this idea, the p-n structure acts as MOSFET by a Virtual Hole’s Well at the source side (VW-SOI MOSFET), so the carrier concentrations specially hole concentration modify in the channel chiefly the source side in ON state which suppresses the floating body effect. The hole concentration, electric field, floating body effect and finally the lattice temperature improve. So the self heating effect that is one of the biggest problems in SOI devices, improves. Also, the simulation results of the VW-SOI MOSFET indicate that it is a suitable case for a switching performance because of decreasing gate-source, gate-drain capacitances, and noise. And finally the proposed structure can be a reliable structure because it decreases the effect of hot carriers due to short channel effects.

Low Insertion Loss, Compact 4-bit Phase Shifter in 65 nm CMOS for 5G Applications

This letter presents a 28 GHz low insertion loss and compact size 4-bit phase shifter in 65 nm CMOS Technology. In order to get low insertion loss and compact size, this phase shifter is composed of two types of passive phase shifters, high-pass/low-pass type and switched filter type. Various techniques are used such as triple well body-floating, gate-floating, removal of capacitance of the off-state transistor using resonant inductor, and minimized interconnection line which is based on matching network. This phase shifter has 6.36 dB of average insertion loss over the 27.5–28.35 GHz, and loss variation is about 2 dB. The return loss is higher than 12 dB, RMS phase error is 8.98 $^{\circ}$ , OIP3 is 8.1 dBm at $-$ 10 dBm input power and its core size is 636 $\mu$ m $\times$ 360 $\mu$ m. To the authors' knowledge, these results are the state of the art in CMOS passive phase shifters in K-band frequency.

The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients (SETs) due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal—oxide semiconductor field-effect transistor (PMOS FET), but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.

Response of a 0.25 μm thin-film silicon-on-sapphire CMOS technology to total ionizing dose

The radiation response of a 0.25 μm silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. The threshold-voltage shift is less than 170 mV and the leakage-current increase is less than 1 nA for individual standard-layout nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.

Large SET Duration Broadening in a Fully-Depleted SOI Technology—Mitigation With Body Contacts

Significant floating body effects were measured in 0.2 μm fully-depleted SOI resulting in large amounts of single event transient (SET) broadening, i.e., SET duration stretching. The transient response of single transistors and the propagation of single-event transients (SET) in chains of logic gate (inverters and NOR gates) were investigated by using either heavy ion irradiation or focused laser pulses. Single transistors displayed a particularly slow recovery after an ion strike (> 100 ns). In logic chains, large amounts of SET duration broadening, up to 30 ps/gate, were measured when the unattenuated rail-to-rail SET propagates to the output of the chain. These floating body effects occur mainly at low frequency. They are induced by the accumulation of majority carriers in the body region which contribute to reduce the threshold voltage of OFF-state transistors. This is a slow phenomenon which takes up to several tenths of a second to build-up. It is demonstrated that floating body effects are reduced when designed with body contacts or when the chain operates at high frequency.

InP HEMT Technology for High-Speed Logic and Communications

As a review of the InP HEMT technology and its applications to logic ICs, the two-step-recess gate structure, which is now widely used in high-performance InP HEMTs, and its application to optoelectronic ICs are described. This paper also covers the topic of the gate delay analysis that reveals that the parasitic delay becomes the primary cause of the gate delay in sub-100-nm gate regime. For future challenge for logic applications, ways to reduce the off-state transistor current is also discussed.

Monte-Carlo simulation of the dynamic behavior of a CMOS inverter struck by a heavy ion

We present a theoretical study using Monte-Carlo simulation of the behavior of a CMOS inverter struck by an ionizing particle. The inverter is made of two complementary enhancement-mode MOSFETs according to a SIMOX self-aligned technology with an effective gate length of 0.35 /spl mu/m. The effect of the ionizing particle (heavy ion) is simulated by electron-hole pairs generation with an energy of 1 eV for each carrier. We studied the return to the steady-state of the device after a transient irradiation. Either the P-channel transistor or the N-channel transistor is irradiated, and the gate operating is considered in both cases of 0 V and 5 V input voltage. The irradiation of the off-state transistors induces a significant transient variation of the output voltage whereas irradiation of the on-state transistors has weak effects on the output. The return to the stationary regime, which is reached after about 50 ps in all irradiation cases, is achieved by evacuation of the carriers in excess through the different electrodes without trapping effect in the device. >