In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space industry. To mitigate the impacts of SEUs and SEMNUs, this paper proposes the Read Stability Improved and Low Power (RSLP16T) SRAM cell. It was confirmed that in SEU-induced simulations, all nodes of the RSLP16T could be restored with a charge amount of less than 100 fC. Additionally, it was verified that a similar level of restoration was possible for SEMNUs occurring in pair of storage nodes. The proposed cell achieves a high level of read stability due to a high pull-down cell ratio (current ratio, CR) at the storage nodes and the fact that only a pair of nodes is in contact with the bit lines during read operations. Because all node paths use a stacking structure for internal transistor configuration and a relatively higher number of cells are composed of PMOS, it consumes the least hold power. While these improvements come at the cost of slightly increased delay time and area, performance evaluation revealed that the equivalent quality metric (EQM) was the highest, indicating that the benefits outweigh the drawbacks. The proposed integrated circuit is implemented in the 90 nm CMOS process and operated on 1 V supply voltage.
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