Transient Charge Trapping Research Articles

Reliability Instability Assessment with Interfacial Trapping Analysis for the Optimization of Al Composition in AlxGa1−xN/GaN High Electron Mobility Transistors

This study investigates the trapping characteristics present at the interface of AlxGa1−xN/GaN high electron mobility transistors (HEMTs) and explores the influence of the Al composition within the AlxGa1−xN barrier on the device's performance. Using a single pulse ID–VD characterization technique, the reliability instability is evaluated in two different AlxGa1−xN/GaN HEMTs: one with an Al composition of 25% (Al0.25Ga0.75N/GaN) and the other with an Al composition of 45% (Al0.45Ga0.55N/GaN). The results unveil a notable higher drain current degradation (ΔID) in Al0.45Ga0.55N/GaN devices, attributed to fast transient charge trapping. Conversely, the Al0.25Ga0.75N/GaN device exhibits a substantial 35% reduction in interface trap density (Dit) and an impressive 73% decrease in border trap density (Nbt), solidifying its reduced trapping behavior compared to Al0.45Ga0.55N/GaN due to the rougher barrier/channel interface of the latter device. Furthermore, load‐pull measurements unveiled a noteworthy 60% power‐added efficiency for the Al0.25Ga0.75N/GaN device, presenting a 10% performance improvement over the Al0.45Ga0.55N/GaN device. These findings provide valuable insights into the trapping phenomena within AlGaN/GaN HEMTs, paving the way for enhanced device design and performance optimization.

Oxygen vacancy related hole fast trapping in high mobility cubic-Ge/ZrO2 interface

Ge has the potential to replace Si as the future field-effect transistors channel material due to its superior hole mobility, and cubic zirconia with high dielectric constant and small lattice mismatch can be selected as its oxide layer. At present, the mechanism of charge trapping caused by defects in the Ge oxide layer interface and bulk of such device has not been accurately analyzed. In our work, we have constructed the cubic Ge/ZrO2 interface, and studied the electronic structure and hole trapping characteristics of the interface structure by first-principles hybrid-functional calculations with Marcus theory. According to research oxygen vacancies with the different distances (abbr. d O-int) away from the Ge substrate, we confirm that the oxygen vacancy can act as a fast trap center to capture the hole of the valence band maximum (VBM) from Ge, resulting in the ultrafast or fast transient charge trapping in the high-k gate dielectric. We found that, when a given range of applied electric field, the hole trap is ultrafast with capture time of 10−6–10−5 when d O-int is within the range of 2–7 , and there is a 2–3 order of magnitude increases in capture time as d O-int exceeds 7 with the maximum capture cross section reducing substantially. Here, our work provides a clear and reasonable description of the distance-dependent hole trapping process at the Ge/high-k dielectrics metal-oxide-semiconductor (MOS) devices and provides significant support for solving the reliability problem of microelectronic devices.

Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part II: The Role of Polarons

Using the framework developed in the first part of this work, we demonstrate the capabilities of the extended two-state nonradiative multi-phonon (NMP) model by reproducing leakage current characteristics of two selected technologies. First, we identify the temperature-activated leakage mechanism in SiC / SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stacks using a tens of nanometer thick thermally grown oxide as trap-assisted tunneling (TAT) through defects. Interestingly, this effect can be reproduced with the same parameters in a SiC / SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stack with deposited oxide. Our simulations demonstrate that these charge transition centers are distributed within only a few nanometers from the SiC / SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. The low thermal activation of the leakage current is linked to the low relaxation energies of the involved traps compared with those typically involved in bias temperature instability (BTI) and Random Telegraph Noise (RTN). Second, a similar mechanism can explain TAT characteristics and transient charge trapping currents in Metal–Insulator–Metal (MIM) capacitors with a ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> insulating layer. By comparison of our model parameters to theoretical density functional theory (DFT) calculations, we identify self-trapped electrons (polarons) as a likely cause for these effects, as they have the required low relaxation energies.

Salt-assisted growth of monolayer MoS2 for high-performance hysteresis-free field-effect transistor

Atomically thin layered materials such as MoS2 have future versatile applications in low power electronics. Here, we demonstrate the growth of a salt-assisted large scale, high-quality monolayer MoS2 toward the realization of a high-performance hysteresis-free field-effect transistor (FET). Density functional theory calculations are implemented to monitor the effects of the Schottky barrier and metal-induced gap states between our metal electrodes and MoS2 for achieving high carrier transport. The role of absorbed molecules and oxide traps on the hysteresis are studied in detail. For the first time, a hysteresis-free intrinsic transistor behavior is obtained by an amplitude sweep pulse I–V measurement with varying pulse widths. Under this condition, a significant enhancement of the field-effect mobility up to 30 cm2 V−1 s−1 is achieved. Moreover, to correlate these results, a single-pulse time-domain drain current analysis is carried out to unleash the fast and slow transient charge trapping phenomena. Our findings on the hysteresis-free transfer characteristic and high intrinsic field-effect mobility in salt-assisted monolayer MoS2 FETs will be beneficial for future device applications in complex memory, logic, and sensor systems.

Transient negative capacitance and charge trapping in FDSOI MOSFETs with ferroelectric HfYOX

Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

Fast and slow transient charging of Oxide Semiconductor Transistors

The comprehension of the governing mechanism which affects device instability is one of the most important requirements for the formation of reliable oxide-thin film transistors (TFTs). However, a quantitative analysis of the dominant mechanism of device instability, which stems from charge trapping induced by defects at the oxide semiconductor interface as well as in its bulk, has not yet been systematically performed. In this study, we examined subgap states, charge-transport dynamics, and various trap characteristics of oxide TFTs by multi-frequency C–V, pulse I–V, and transient current methods to achieve a comprehensive understanding of carrier transport and charge trapping mechanisms. We found that the charge trapping behavior of the tested amorphous InHfZnO (a-IHZO) TFT follows a multi-trapping mechanism, such as temperature-independent fast transient charge trapping by resonant drift of the injected electron and temperature-dependent slow transient charge trapping by charge transport from occupied to unoccupied traps. Understanding fast charging and slow charging described in this study can help to understand the root cause of device instability of oxide TFTs and ultimately improve stability and reliability characteristics.

Microsecond Pulse I\u2013V Approach to Understanding Defects in High Mobility Bi-layer Oxide Semiconductor Transistor

The carrier transport and device instability of amorphous oxide semiconductor devices are influenced by defects that are exponentially distributed in energy, because of amorphous phase channels and front/back interfaces with a large number of sub-gap states. Thus, understanding defects and charge trapping in oxide semiconductor transistors is required for being core device element in reliable production lines. In this paper, we present the transient charging effect, the charge trapping mechanism, and the dynamic charge transport of high-mobility bilayer oxide semiconductor transistors. To this end, we exploited microsecond ramps, pulse ID–VG, transient current, and discharge current analysis methods. The mobility enhancement rate of single HfInZnO (HIZO) and bilayer HfInZnO-InZnO (HIZO-IZO) were 173.8 and 28.8%, respectively, in the charge-trapping-free environment. Transient charge trapping can be classified to temperature insensitive fast charging and thermally activated slow charging with two different trap energies. Insignificant fast transient charging of a bilayer-oxide high-mobility thin film transistor(TFT) can be explained by the low density of sub-gap states in the oxide semiconductor. Understanding defects and transient charging in the oxide semiconductor helps to determine the origin of device instability of oxide TFTs, and finally, to solve this problem.

Determination of intrinsic mobility of a bilayer oxide thin-film transistor by pulsed I–V method

Amorphous oxide semiconductor thin-film transistors (TFT) have been considered as outstanding switch devices owing to their high mobility. However, because of their amorphous channel material with a certain level of density of states, a fast transient charging effect in an oxide TFT occurs, leading to an underestimation of the mobility value. In this paper, the effects of the fast charging of high-performance bilayer oxide semiconductor TFTs on mobility are examined in order to determine an accurate mobility extraction method. In addition, an approach based on a pulse I D –V G measurement method is proposed to determine the intrinsic mobility value. Even with the short pulse I D –V G measurement, a certain level of fast transient charge trapping cannot be avoided as long as the charge-trap start time is shorter than the pulse rising time. Using a pulse-amplitude-dependent threshold voltage characterization method, we estimated a correction factor for the apparent mobility, thus allowing us to determine the intrinsic mobility.

Effect of hydrogen on dynamic charge transport in amorphous oxide thin film transistors

Hydrogen in zinc oxide based semiconductors functions as a donor or a defect de-activator depending on its concentration, greatly affecting the device characteristics of oxide thin-film transistors (TFTs). Thus, controlling the hydrogen concentration in oxide semiconductors is very important for achieving high mobility and minimizing device instability. In this study, we investigated the charge transport dynamics of the amorphous semiconductor InGaZnO at various hydrogen concentrations as a function of the deposition temperature of the gate insulator. To examine the nature of dynamic charge trapping, we employed short-pulse current−voltage and transient current−time measurements. Among various examined oxide devices, that with a high hydrogen concentration exhibits the best performance characteristics, such as high saturation mobility (10.9 cm2 v−1 s−1), low subthreshold slope (0.12 V/dec), and negligible hysteresis, which stem from low defect densities and negligible transient charge trapping. Our finding indicates that hydrogen atoms effectively passivate the defects in subgap states of the bulk semiconductor, minimizing the mobility degradation and threshold voltage instability. This study indicates that hydrogen plays a useful role in TFTs by improving the device performance and stability.

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO2 gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (VO−Oi) – could consistently explain the experimental observations. An interesting feature of the VO−Oi defect is that it can exists in various metastable configurations with the interstitial oxygen Oi in different positions around the vacancy VO, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.

Charge trapping induced frequency-dependence degradation in n-MOSFETs with high-k/metal gate stacks

This letter investigates the reliability issues of HfO 2/Ti 1 − x N x metal-oxide-semiconductor field effect transistor in terms of static and dynamic stress. The results indicate threshold voltage ( V th ) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. Capacitance–voltage techniques verified that electron trapping under dynamic stress was located in high-k dielectric near the source/drain (S/D) overlap region, rather than the overall dielectric. Furthermore, the V th shift clearly increases with an increase in dynamic stress operation frequency. This phenomenon can be attributed to the fact that electrons injecting to the S/D overlap region have insufficient time to de-trap from high-k dielectric. We further investigated the impact of different Ti 1 − x N x composition of metal-gate electrode on charge trapping characteristics, and observed that V th shift decreases significantly with an increase in the ratio of nitride. This is because the nitride atoms diffusing from the metal gate fill up oxygen vacancies and reduce the concentration of traps in high-k dielectric.

Physical and Numerical Modelling for Bipolar Charge Transport in Disorder Polyethylene Under High DC Voltage

This paper reports on validation of a numerical model for both transient and steady bipolar charge transport, trapping and recombination in polymeric insulators, such as low density polyethylene. The numerical model is based on the high precision Runge-Kutta method for determining mobile and trapped charge local density within the sample, during the application of a DC voltage. In addition, we have applied the finite element method considered as the most general one, which can be applied to any sample shape and boundary conditions. It is applied to resolve Poisson's equation, thus providing the potential and its gradient within the sample and at the dielectric-electrode interfaces. The principal results show the appearance of charge packets for the first time in modeling works although they have long been reported in experimental studies on polyethylene materials. The conditions for the appearance of such packets are discussed. For the net space charge density and the conduction current, the dynamics are in a good agreement with those observed in some experimental works during the transit time of the bipolar carriers. The model is already numerically validated for the space charge densities and the electric field distribution under low DC voltage.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-κ dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trapinduced threshold voltage shift (△VSUBt/SUB), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-κ gate dielectric devices.

Transient charge trapping and detrapping properties of a thick SiO2/Al2O3 stack studied by short single pulse Id-Vg

The transient charge trapping and detrapping of a thick SiO2/Al2O3 gate oxide device has been evaluated by single pulse Id-Vg (PIV). During the period of a single pulse, we observed fast electron detrapping. This occurred through the gate electrode, causing a counterclockwise PIV hysteresis despite electron injections from the channel region. The hysteresis direction transitioned from counterclockwise to clockwise as a function of pulse base level and peak level. The trap energy level of Al2O3, extracted by PIV at various temperatures, was found to be in the range of 1.14–1.39 eV, indicating the Frenkel–Poole defect band.

Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast $I$–$V$ Techniques

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2 interface is proposed.

The influence of HfO 2 film thickness on the interface state density and low field mobility of n channel HfO 2/TiN gate MOSFETs

The influence of HfO 2 thickness (1.6 to 3nm) on interface state density and low field mobility in HfO 2/TiN gate n channel MOSFETs have been studied by analyzing experimental data from charge pumping, split CV, DC I d- V g, pulsed I d- V g and Y-function methods. It is found that there is no HfO 2 thickness dependence on the interface state density, whereas there is continuous electron mobility degradation with HfO 2 thickness. The devices exhibited no detectable fast transient charge trapping, allowing the relative contributions of phonon and Coulomb scattering to be examined over temperature. The dependence of the low field mobility on temperature from 50 K to 400 K indicates HfO 2 remote phonon scattering as the dominant cause of the mobility degradation.

CMOS Device and Circuit Degradations Subject to $\hbox{HfO}_{2}$ Gate Breakdown and Transient Charge-Trapping Effect

The gate leakage current of HfO2 MOSFETs exhibits the power law characteristics after soft breakdown (BD) and the linear behavior after hard BD. Fast transient charge-trapping effect (FTCTE) shifts the inverter transfer characteristics but does not affect the high and low output voltages. The ring oscillator remains functional after gate BD. The BD position near the drain end of the n-channel transistor increases the noise figure (NF) significantly, whereas FTCTE has minor impact on the NF of the folded cascode low-noise amplifier

Transient Charge Trapping in Eu 3+ -Doped Nanocomposites by Ultrafast Laser Excitation

Eu 3+ was incorporated as probe ions into nanocomposite glasses, such as metal silver doped phosphate glass and crystalline nanocomposites Si-enriched SiO 2 glass. Luminescence studies show that the doped europium ions are present as trivalent Eu 3+, and are distributed in the matrix on the boundary surface of nanoparticles. The valence switching from Eu 3+ to Eu 2+ was observed in Si-SiO 2 nanocomposites when ultrafast laser excitation was applied. In silver metal nanoparticles embedded aluminophosphate glass, a time-resolved ultrafast degenerate-four-wave-mixing (DFWM) experiment shows enhanced third-order nonlinearity at zero-delay time, followed by a bell-like signal buildup. It is attributed to the creation of electronic polaron and vibronic Wannier-Mott exciton (WME). In europium codoped sample, however, the bell-like signal is depressed. All the above observations are interpreted as the result of a strong Coulomb interaction between conduction electrons produced inside the nanoparticles by laser excitation and Eu 3+ ions residing near the boundary surface. The trivalent europium ions play the role as positive charges attracting electrons. This results in temporary formation of Eu 2+, and blocks the resonant tunneling transition in the silver-glass system to avoid creating large radius polaron.

Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.