Transfer Characteristics Of Transistors Research Articles

Reversible Carrier Concentration Control on Ultra-Thin in2O3 By Viologen Molecules Charge Transfer Method

Ultra-thin Oxide semiconductor fabricated by atomic layer deposition (ALD) is one of the promising candidates, due to their ultra-thin thickness and being highly compatible with the silicon process.[1] However, further tuning the oxide semiconductor's carrier concentration is still an interesting issue. Although annealing is a widely used way, the increase in thermal budget is unwilling to be met. To adjust the carrier concentration without increasing the thermal budget, viologen molecule, a strongly n-type dopant which have been successfully applied to different material systems including 2D,[2] CNT,[3] ultra-thin Ⅲ-Ⅴ,[4] has been used in the In2O3 transistor(as shown in Figure 1a). After viologen treatment, the viologen dopants increased the carrier concentration and caused a difference of n 2D, which is 2 × 1012 cm-2 of 2 nm thickness in In2O3, without degrading the mobility under the same overdrive voltage. The In2O3 transistor achieves an electron sheet density of 6.8 × 1012 cm−2. To further expand the function, viologen dopants are modified by hydroxy group. With hydroxy group modifying, the viologen dopants can be removed by acetone and be re-treated back on the In2O3 again. The reversible cycle of viologen treatment can be repeated multiple times without harming the In2O3 device (as shown in Figure 1b). Precise control of the threshold voltage allows for fine-tuning of the transistor between depletion mode and enhancement mode. Based on this, a depletion load inverter has been demonstrated. This result shows that the viologen dopants and In2O3 have the potential to be further integrated with other low dimensional materials in BEOL without raising the thermal budget while tuning the carrier concentrations. Figure 1. a) Schematic representation of the structure of a In2O3 bottom-gate transistor and the viologen charge transfer process. b) The transfer characteristics of In2O3 transistors repeatedly treated and removed of OHV for four cycles. References (1) Si, M.; Lin, Z.; Chen, Z.; Sun, X.; Wang, H.; Ye, P. D. Scaled Indium Oxide Transistors Fabricated Using Atomic Layer Deposition. Nat. Electron. 2022, 5 (3), 164-170. DOI: 10.1038/s41928-022-00718-w.(2) Kiriya, D.; Tosun, M.; Zhao, P.; Kang, J. S.; Javey, A. Air-Stable Surface Charge Transfer Doping of MoS2 by Benzyl Viologen. J. Am. Chem. Soc. 2014, 136 (22), 7853-7856. DOI: 10.1021/ja5033327.(3)Kim, S. M.; Jang, J. H.; Kim, K. K.; Park, H. K.; Bae, J. J.; Yu, W. J.; Lee, I. H.; Kim, G.; Loc, D. D.; Kim, U. J.; Lee, E.-H.; Shin, H.-J.; Choi, J.-Y.; Lee, Y. H. Reduction-Controlled Viologen in Bisolvent as an Environmentally Stable n-Type Dopant for Carbon Nanotubes. J. Am. Chem. Soc. 2009, 131 (1), 327-331. DOI: 10.1021/ja807480g.(4) Takei, K.; Kapadia, R.; Li, Y.; Plis, E.; Krishna, S.; Javey, A. Surface Charge Transfer Doping of III–V Nanostructures. J. Phys. Chem. C 2013, 117 (34), 17845-17849. Figure 1

Characteristics of Fully-Depleted Poly-Si Thin Film Transistors Operated in Above-Threshold Region with Low Drain Bias

Transfer and output characteristics of fully-depleted polycrystalline silicon thin film transistors, including both tail and deep acceptor-like trap states in bulk, in the above-threshold region with low drain bias are presented under low or high state density in the situation without or with interface charge, respectively. The characteristics are calculated by a simple surface-potential-based drain current model in the strong inversion region with valid bias condition explained, and 2D-device simulation. The above-threshold region is found to be divided into Regions I and II, with Vsi , indicating the channel beginning to be completely strongly-inverted and large currents, and explication of deviations between the model and simulation in Region I. The large-traps effect on the range of Region I and Vth in the high state density situation is discovered.

Tuning Gate Potential Profiles and Current-Voltage Characteristics of Polymer Electrolyte-Gated Transistors by Capacitance Engineering.

We demonstrate that the transfer characteristics of electrolyte-gated transistors (EGTs) with polythiophene semiconductor channels are a strong function of gate/electrolyte interfacial contact area, i.e., gate size. Polythiophene EGTs with gate/electrolyte areas much larger than the channel/electrolyte areas show a clear peak in the drain current vs gate voltage (ID-VG) behavior, as well as peak voltage hysteresis between the forward and reverse VG sweeps. Polythiophene EGTs with small gate/electrolyte areas, on the other hand, exhibit current plateaus in the ID-VG behavior and a gate-size-dependent hysteresis loop between turn on and off. The qualitatively different transport behaviors are attributed to the relative sizes of the gate/electrolyte and channel/electrolyte interface capacitances, which are proportional to interfacial area. These interfacial capacitances are in series with each other such that the total capacitance of the full gate/electrolyte/channel stack is dominated by the interface with the smallest capacitance or area. For EGTs with large gates, most of the applied VG is dropped at the channel/electrolyte interface, leading to very high charge accumulations, up to ∼0.3 holes per ring (hpr) in the case of polythiophene semiconductors. The large charge density results in sub-band-filling and a marked decrease in hole mobility, giving rise to the peak in ID-VG. For EGTs with small gates, hole accumulation saturates near 0.15 hpr, band-filling does not occur, and hole mobility is maintained at a fixed value, which leads to the ID plateau. Potential drops at the interfaces are confirmed by in situ potential measurements inside a gate/electrolyte/polymer semiconductor stack. Hole accumulations are measured with gate current-gate voltage (IG-VG) measurements acquired simultaneously with the ID-VG characteristics. Overall, our measurements demonstrate that remarkably different ID behavior can be obtained for polythiophene EGTs by controlling the magnitude of the gate-electrolyte interfacial capacitance.

Effect of Transistor Transfer Characteristics on the Programming Process in 1T1R Configuration

Effect of Transistor Transfer Characteristics on the Programming Process in 1T1R Configuration

Selected Area Manipulation of MoS2 via Focused Electron Beam-Induced Etching for Nanoscale Device Editing.

We demonstrate direct-write patterning of single and multilayer MoS2 via a focused electron beam-induced etching (FEBIE) process mediated with the XeF2 precursor. MoS2 etching is performed at various currents, areal doses, on different substrates, and characterized using scanning electron and atomic force microscopies as well as Raman and photoluminescence spectroscopies. Scanning transmission electron microscopy reveals a sub-40 nm etching resolution and the progression of point defects and lateral etching of the consequent unsaturated bonds. The results confirm that the electron beam-induced etching process is minimally invasive to the underlying material in comparison to ion beam techniques, which damage the subsurface material. Single-layer MoS2 field-effect transistors are fabricated, and device characteristics are compared for channels that are edited via the selected area etching process. The source-drain current at constant gate and source-drain voltage scale linearly with the edited channel width. Moreover, the mobility of the narrowest channel width decreases, suggesting that backscattered and secondary electrons collaterally affect the periphery of the removed area. Focused electron beam doses on single-layer transistors below the etching threshold were also explored as a means to modify/thin the channel layer. The FEBIE exposures showed demonstrative effects via the transistor transfer characteristics, photoluminescence spectroscopy, and Raman spectroscopy. While strategies to minimize backscattered and secondary electron interactions outside of the scanned regions require further investigation, here, we show that FEBIE is a viable approach for selective nanoscale editing of MoS2 devices.

Simulation and optimization of metal gate CMOS process and circuit by TCAD

The feature size of CMOS transistors is shrinking as the semiconductor industry and technology advance. This phenomenon will have significant research implications for how to change device performance and maintain good performance. As a result, this paper completed a design and simulation of the CMOS process flow using TCAD. It was discovered through a qualitative analysis of the simulation results that the transfer and input characteristics of NMOS transistors decrease proportionally with the scale factor.

Dependence of the Transfer Characteristics of Metal-Oxide Thin-Film Transistors on the Temperature of an Extended Oxidizing Heat-Treatment

When a metal-oxide (MO) thin-film transistor (TFT), specifically that based on indium-gallium-zinc oxide (IGZO), is subjected to an oxidizing heat-treatment, its transfer characteristic is found to exhibit a parallel shift that depends on the temperature and saturates upon an extended heat-treatment. Presently a model governing the oxidation and reduction kinetics of donor-defects is applied to describe the observed temperature dependence. Quantified by the change in the saturated turn-on voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {ON}\text {Sa}\text {t}}}$ </tex-math></inline-formula> ), the parallel shift of the transfer characteristic of a TFT after an extended oxidizing heat-treatment in the temperature range from 300 to 450 °C can be precisely predicted by measurable model parameters. These results further illustrate the utility of the model as a tool for developing and optimizing MO TFT technologies by controlling <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {V}_{{\text {ON}\text {Sa}\text {t}}}$ </tex-math></inline-formula> .

Charge Transfer Dynamics of Doped Graphene Electrodes for Organic Light-Emitting Diodes.

Atomically thin graphene has attracted immense attention as a future transparent electrode for flat-panel displays owing to its excellent conductivity, optical transparency, and flexibility. In particular, a graphene doping process is essential for implementing graphene-based high-performance devices, and the development of a transparent cathode with a low work function is required to simplify the integration process of thin-film transistors and organic light-emitting diodes (OLEDs) into active matrix displays. In this study, a transparent n-doped graphene cathode is proposed for implementing inverted OLEDs through two types of cesium (Cs)-based doping techniques: a dipping method using wet chemicals and an evaporation method under a vacuum atmosphere. The changes in the chemical structures and work functions of the n-doped graphene electrodes, as well as their surface morphologies and transmittances, were systematically investigated. The n-type doping mechanism of graphene was investigated, and a close relationship between the electrical charge transfer characteristics of graphene transistors and the formation of C-O-Cs complexes was revealed. Finally, an effective Cs-doped graphene electrode was developed, exhibiting a dramatically decreased work function while maintaining high transmittance; therefore, the Cs-doped graphene cathode was successfully integrated with inverted OLEDs with a bottom-light emission structure that exhibited enhanced external quantum efficiency of graphene cathode-based OLEDs. Thus, our findings provide a better understanding of the doping strategies and potential of n-doped graphene as a transparent cathode for developing high-performance future displays.

Synergy effect of microwave annealing and high-pressure hydrogen annealing on Poly-Si thin-film transistor

Grain boundary (GB) is a significant factor that deteriorates the transfer characteristics of poly-Si thin-film transistors (TFTs). In this study, we utilized the synergistic effect of microwave annealing (MWA) and high-pressure hydrogen annealing (HPHA) to effectively reduce grain boundary trap (GBT) density, resulting in improved field-effect mobility (μ) and subthreshold swing (SS). To investigate the synergistic effect of MWA and HPHA, the transfer characteristics of rapid thermal annealing and forming gas annealing devices were compared and analyzed as control devices. Furthermore, the mechanism of SS and mobility enhancement can be quantitatively understood by lowering the GB barrier height. In addition, Raman spectroscopy proved that poly-Si crystallinity was improved during MWA. Our results showed that MWA and HPHA play a vital role in reducing GBT density and improving poly-Si TFT characteristics.

Raman Spectroscopy-Assisted Characterization of Nanoform MoS2 Thin Film Transistor.

In this paper, we report the simple preparation and investigation of electrical transport properties of nanoform MoS2 thin film transistor (TFT) devices. MoS2 nanoparticles were synthesized by using the hydrothermal method. The physiochemical characterizations such as UV-vis, Fourier transform infrared, X-ray diffraction, and Raman spectroscopy studies were performed. Spin-coating was used to make the thin film on which silver electrodes were made. We observed nonlinear current-voltage (I-V) characteristics; however, the symmetricity was found in the I-V curve which confirms the no formation of the Schottky barrier between thin film and electrodes. Transistor transfer characteristics reveal that the TFT device is n-doped as more drain current modulation is observed when the positive gate voltage is applied. The relationship between gate-current and gate voltage studies concludes that there is no leakage gate current in the TFT device which further confirms the good reliability of transfer characteristics of a device. The device mobility was calculated as ~10.2 cm2/Vs, and the same was explained with plausible reason supported with Raman spectra analysis.

Dedicated to the memory of V.D. Aleksandrov Effect of annealing in an inert atmosphere on the electrical properties of crystalline pentacene films

The results of a study of the effect of annealing at 150^oC in an inert atmosphere (Ar + 5% H2) on the electrical properties of organic field-effect transistors based on pentacene are presented. Crystalline pentacene films with a thickness of 95±5 nm were obtained using thermal vacuum deposition. The transfer and output characteristics of field-effect transistors before and after annealing for 15 hours are investigated. It was found that as a result of heat treatment, the hole mobility in the saturation regime increased by an average of 30%, and the threshold voltage decreased approximately two times. According to the data of atomic force microscopy, annealing led to a more than twofold decrease in the surface roughness of pentacene films, as well as to a noticeable enlargement of grains, which led to a decrease in the concentration of traps for hole electric transport in the channel of the field-effect transistor. Keywords: pentacene, vacuum thermal deposition, crystalline films, organic field-effect transistors, hole mobility, annealing in an inert atmosphere.

Influences of vacuum annealing induced oxygen defects on the transfer characteristics of a-ITO thin-film transistors

Amorphous indium–tin-oxide (a-ITO) films are fabricated by pulsed laser deposition at room temperature and annealed in vacuum. Although vacuum annealing could ameliorate the carrier mobility and subthreshold swing, the threshold voltage shows a negative shift upon vacuum annealing at 450 K, and a hump emerges in the subthreshold region. The density of electronic states extracted by Grünewald method demonstrate that the hump is caused by shallow donor-like states. Furthermore, the X-ray photoelectron spectra and the photoconductivity experiment reveal that the shallow donors are ascribed to the increased oxygen defects upon thermal annealing.

A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.

Charge distribution in turbostratic few-layer graphene studied by carbon isotope labeling

Elucidating layer-resolved charge distribution in van der Waals stacked crystals is crucial for electronic applications based on 2D materials. Here, we use CVD-grown few-layer graphene (FLG) labeled by carbon isotopes as a prototype, in which Raman features of two isotope components identify distinct layers. Electrical transfer characteristics of graphene field-effect transistors (GFETs) are employed to quantitatively calibrate the correspondence of Fermi level and G-phonon frequency that shifts with the charge-carrier concentration (n) variation. The isotope-assisted spectroscopy reveals previously unprobed characteristics that the n value of both top and bottom layers in FLG is close rather than following an exponential decay law. This negligible gradient likely benefits from the π−π interaction that favors the interlayer diffusion of charges. In addition, each extra layer reduces the degree of charge exchange at the graphene/dopant interface. These results have important implications for FLG nanoelectronics and provide a robust framework by which one can further investigate the critical properties of other 2D systems.

Self-Heating Stress-Induced Severe Humps in Transfer Characteristics of Amorphous InGaZnO Thin-Film Transistors

Under a self-heating stress (SHS), amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) would exhibit a severe hump in the transfer characteristics. A model based on state transformation of oxygen vacancies is proposed to explain this phenomenon. The channel region of TFT is considerably self-heated if a large current flows through due to the poor thermal conductivity of a-IGZO. The temperature in the channel region can be raised with the high-power SHS so high that the oxygen vacancies there perform a state transformation from deep-donors and/or traps to shallow-donors, making the carrier concentration increase remarkably in the a-IGZO channel layer. The temperature is highest in the center of channel region and thus the state transformation takes place there first, leading to the carrier concentration increasing there first. As a result, the TFT has a lower turn-on voltage in the central channel region than in the rest, bringing finally about the hump in the transfer curves. The model is well verified by annealing the a-IGZO, which shows that the carrier concentration surely increases greatly when the annealing temperature is over 300 °C.

Alignment of linear polymeric grains for highly stable N-type thin-film transistors

Summary Temperature-insensitive properties are attractive for most electronics, including polymeric semiconducting devices. Especially, polymeric field-effect transistors (FETs) with high mobility have been important research targets due to their broad applications. However, polymeric FETs with stable charge transport operating at extremely cold or hot zones are faced with enormous challenges. In this study, the polyacrylonitrile was found to significantly tune the sizes of pre-aggregates of polymers in solutions and the crystallinity of the polymeric films. The orientation of 5–25 μm linear grains in the films were prepared through the bar-coating process with polyacrylonitrile as an additive, which stabilized the electron mobility over a wide range of temperatures. The linear-grain morphology of the film contributed to reducing the holes and grain boundaries in the transport paths of carriers. Typically, the top-gate FETs based on P(NDI2OD-T2) displayed a stable electron transporting behavior from 200 to 460 K, with mobility greater than 3.5 cm2V−1s−1.

Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS2 Field-Effect Transistors.

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS2 channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS2 FETs using a gate-drain underlap design to induce a differential response from traps near the MoS2-HfO2 channel-gate dielectric interface, also referred to as border traps, to applied gate bias. The appearance of trap-driven anticlockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS2 channel flake. The underlap design also enables room temperature tuning of the anticlockwise hysteresis window (by 140×) as well as the crossover gate voltage (by 2.6×) with applied drain bias and underlap length. Comprehensive measurements of the transfer curves in ambient and vacuum conditions at varying sweep rates and temperatures (RT, 45 °C, and 65 °C) help segregate the quantitative contributions of adsorbates, interface traps, and bulk HfO2 traps to the clockwise and anticlockwise hysteresis.

Combining Chemical Functionalization and FinFET Geometry for Field Effect Sensors as Accessible Technology to Optimize pH Sensing

Field Effect Transistors (FETs) have led the progress of applications measuring the acidity in aqueous solutions thanks to their accuracy, ease of miniaturization and capacity of multiplexing. The signal-to-noise ratio and linearity of the sensors are two of the most relevant figures of merit that can facilitate the improvements of these devices. In this work we present the functionalization with aminopropyltriethoxysilane (APTES) of a promising new FET design consisting of a high height-to-width aspect ratio with an efficient 2D gating architecture that improves both factors. We measured the transistor transfer and output characteristics before and after APTES functionalization, obtaining an improved sensitivity and linearity in both responses. We also compared the experimental results with a site-biding model of the surface buffering capacity of the APTES functionalized layers.

Посвящается памяти В.Д. Александрова Влияние отжига в инертной атмосфере на электрические свойства кристаллических пленок пентацена

The results of a study of the effect of annealing at 150 °C in an inert atmosphere (Ar + 5% H2) on the electrical properties of organic field-effect transistors based on pentacene are presented. Crystalline pentacene films with a thickness of 95 ± 5 nm were obtained using thermal vacuum deposition. The transfer and output characteristics of field-effect transistors before and after annealing for 15 hours are investigated. It was found that as a result of heat treatment, the hole mobility in the saturation regime increased by an average of 30%, and the threshold voltage decreased approximately two times. According to the data of atomic force microscopy, annealing led to a more than twofold decrease in the surface roughness of pentacene films, as well as to a noticeable enlargement of grains, which led to a decrease in the concentration of traps for hole electric transport in the channel of the field-effect transistor.

Analysis of Transfer Characteristics of InGaZnO Thin Film Transistors

Analysis of Transfer Characteristics of InGaZnO Thin Film Transistors