Total Ionizing Dose Response Research Articles

Characteristics and ultra-high total ionizing dose response of 22 nm fully depleted silicon-on-insulator

The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2) with different back-gate bias configurations, from -8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

TID response of hybrid FinFET with modified gate dielectric

The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose.

Total ionizing dose response of 128 analog states in computational charge-trap memory

Total ionizing dose response of 128 analog states in computational charge-trap memory

Enhanced Total Ionizing Dose Response of 16 nm n-FinFETs With a Single Fin

Enhanced Total Ionizing Dose Response of 16 nm n-FinFETs With a Single Fin

SOI FinFET Design Optimization for Radiation Hardening and Performance Enhancement

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETsf process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFETfs experimental data (error < 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift (VTH) induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas VTH is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the ION/IOFF after radiation increases to 1 × 107, which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.

Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors

Total-ionizing-dose (TID) effects are evaluated in back-gated IGZO thin-film transistors irradiated under different gate biases. Negative-bias irradiation leads to worst-case degradation of TID response in these devices, primarily as a result of enhanced charge trapping in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> overlayer. The relatively small peak transconductance decrease after irradiation illustrates that IGZO transistors are much less sensitive to interface-trap buildup and other instabilities due to hydrogen release and transport than amorphous Si thin film transistors examined previously. The TID response of devices with different gate sizes is also investigated. No significant geometry dependence is observed, which is promising for future scaling down of the technology.

Study of the Within-Batch TID Response Variability on Silicon-Based VDMOS Devices

Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied by the 60Co gamma-ray irradiation experiment in this paper. The variations in device parameters after irradiation is obtained, and the damage mechanism is revealed. Experimental results show that the standard deviations of threshold voltage, subthreshold swing, output capacitance, and diode forward voltage increase, while the standard deviation of maximum transconductance decreases after irradiation. The standard deviation of on-state resistance is basically unchanged before and after irradiation. By separating the trapped charges generated by TID irradiation, it is found that the deviation of the oxide trapped charges and the interface traps increase with the increase in the total dose. The reasons for the variation in device parameters after irradiation are revealed by establishing the relationship between the trapped charges and the electrical parameters before and after irradiation.

Simulation of a ring oscillator operation during γ-ray irradiation using the TID response model of MOSFETs and its experimental verification

The response of N-type MOSFET characteristics to TID (Total Ionizing Dose) effects caused by γ-ray irradiation was modeled as a sum of two exponential functions which expresses the charge accumulation of the oxide traps and the interface traps respectively. This model was applied to the circuit simulation of a ring oscillator operation. It was shown that the simulation result reproduces the variation in the measured oscillation frequency experimentally. The simulation also showed that there is an optimum size ratio between N-type MOSFET and P-type MOSFET which can minimize the variation in oscillation frequency due to TID effects. These obtained results verified that the proposed method can be applied to the prediction of response in a dynamic operation circuit to TID effects.

Bias Dependence of Total Ionizing Dose Response in UTBB FD-SOI Transistors

The impact of continuous bias on the ultra-thin body and buried oxide fully-depleted silicon-on-insulator (UTBB FD-SOI) transistors during total ionizing dose (TID) irradiation is investigated by a device with the single transistor or multiple transistors in parallel. Experimental data of the single transistor shows that the TID bias effect is masked by TID response variation caused by process fluctuation between devices. While the device with multiple transistors in parallel still exhibits a similar TID bias effect as the traditional SOI transistor (TG > OFF > Ground > ON), the process fluctuations between devices are well controlled. Focusing on UTBB FD-SOI parallel transistors, by comparing the results of various bias conditions, the impacts of the drain, gate, and back-gate bias on the TID response of transistors are summarized in detail. Particularly, applying both positive and negative back-gate bias to transistors during TID radiation can obviously increase the TID damage of UTBB FD-SOI parallel transistors, which should be considered in the TID mitigation technique through dynamic back-gate bias. Combined with TCAD simulation, the generation process of oxide-trapped charges in buried oxide (BOX) under different biases is discussed. And, bias dependence of TID response is analyzed from three aspects: fraction of holes escaping initial recombination, holes capture cross section, and spatial distribution of oxide trapped charges. Finally, the TID mitigation calibration law of pMOSFETs is investigated by the empirical model of the back-gate radiation bias effect.

Experimental study of total ionizing dose effect on SiC MOSFETs at temperature from −233 °C to 175 °C

The influence of temperature on the total ionizing dose response of silicon carbide (SiC) metal-oxide-semiconductor filed effect transistors (MOSFETs) was experimentally studied by γ-rays irradiation at temperatures ranging from −233 °C to 175 °C. Electrical parameters were investigated with Current-Voltage (I-V) measurements. Results showed that the threshold voltage shifted toward negative post-irradiation due to the radiation-induced oxide trapped charges. The shift of threshold voltage was a function of irradiation temperature. The shift of threshold voltage increased as temperature decreased. The reason was that there were less annealing for the radiation-induced oxide trapped charges at low temperatures.

Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices

This article provides a brief overview and perspective on the radiation response of nanoscale metal–oxide–semiconductor (MOS) devices. MOS total-ionizing-dose (TID) response is affected strongly by size scaling and the migration from planar to three-dimensional architectures. Radiation-induced charge trapping in isolation oxides and/or charge transport from surrounding materials are critical to the TID response of nanoscale MOS devices. As transistor dimensions and operating voltages have decreased, single-event effects due to cosmic rays and high-energy protons in space and neutrons in terrestrial environments have become increasingly significant to the radiation response of MOS devices. However, nanoscale MOS transistors are essentially immune to ion-induced gate rupture at normal operating voltages. Single-particle interactions will become even more important for future, ultimately scaled MOS devices used in classical and quantum computing applications.

Effects of Layer-to-Layer Coupling on the Total-Ionizing-Dose Response of 3-D-Sequentially Integrated FD-SOI MOSFETs

Total-ionizing-dose (TID) responses are investigated for 3-D-sequentially integrated fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Strong layer-to-layer coupling of TID response is observed. The simultaneous application of positive bias to the gate of the bottom-layer device and negative bias to the top-layer device leads to the maximum enhancement of positive charge trapping in the top-layer device and the intermediate dielectric layer. This enhancement is due to the upward-directed electric field in the intermediate dielectric layer under these bias conditions. In contrast, electrostatic shielding prevents the gate bias of the top-layer device from affecting the response of the bottom-layer device, as confirmed by experiments and technology computer-aided design (TCAD) simulations. Effects of layer-to-layer coupling are less significant for postirradiation-biased annealing.

Influence of LDD spacers on total ionizing dose response of the transconductance for bulk MOSFETs working at cryogenic temperatures

In this work, the radiation responses of 0.25 μm bulk transistors irradiated up to 300 krad are discussed. The electricals characteristics shown are measured after irradiation at 95 K, 150 K, and 300 K. The transconductance improves significantly with total ionizing dose (TID) at low temperature and does not vary at room temperature. The impact of incomplete ionization of impurities introduced into the Lightly Doped Drain extensions is examined. Since the transconductance increase is more pronounced for the shortest transistors, positive charges trapped in spacer oxides are likely to constitute the source of this increase. The Technology Computer-Aided Design simulations help us to discuss the influence of charge build-up at the spacers' locations on the drain to source resistance. By the means of a resistivity analysis, the influence of LDD doping level and operating temperature on the TID response of devices is analyzed. Its potential evolution with technological integration is investigated.

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction modulation is presented and evaluated. The gate metal workfunction is linearly modulated from source to drain to maintain the electrostatic integrity of the device. At the higher radiation dose (2000 krad), the proposed device has shown reduced Off-current by 2-decade leads to improvement in current switching ratio. Moreover, the proposed device offers 9% and 3% improvement in subthreshold swing before and after the radiation, respectively. During irradiation the trap charges are found in the BOX layer and SiO2/Si interface. These charges contributed towards shifting of threshold voltage (Vth). The linear workfunction modulation shows a 73% more Vth as compared to single workfunction FinFET for radiation of 2000 krad dose. As per simulation results, the proposed device is reliable and capable to sustain in the radiation environment.

ASET and TID Characterization of a Radiation Hardened Bandgap Voltage Reference in a 28-nm Bulk CMOS Technology

Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability.

Application of Total Ionizing Dose Radiation Test Standards to SiC MOSFETs

The total ionizing dose (TID) test standards have been developed based on silicon devices to evaluate the TID response of MOS devices for space use. To estimate the applicability of the existing TID test standards to the wide-gap semiconductor silicon carbide (SiC) devices, 1200 V SiC n-channel MOSFETs from three manufacturers were irradiated with Cobalt-60 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -rays at the high radiation dose rate of 50 rad(Si)/s and the low radiation dose rate of 0.01 rad(Si)/s, respectively. The threshold voltage of devices under test (DUT) shifted toward negative due to the radiation-induced positive oxide trapped charges. Room temperature (RT) anneal of maximum time of 2100 h and high temperature (HT) accelerated anneal of maximum temperature of 105 °C were performed, causing the threshold voltage shift to recover. The synergetic effects of temperature-gate-bias stress and TID on SiC MOSFETs were experimentally studied. In conclusion, the degradation of SiC MOSFETs irradiated at high dose rate is dominated by the positive trapped oxide charges, and the existing TID test standards are applicable to evaluate the SiC MOSFETs radiation hardness level, but the threshold voltages shift due to HT-gate-bias (HTGB) should be evaluated.

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Total Ionizing Dose Radiation Effects Hardening Using Back-Gate Bias in Double-SOI Structure

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat.

Effect of Frequency on Total Ionizing Dose Response of Ring Oscillator Circuits at the 7-nm Bulk FinFET Node

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ).

Influence of Fin and Finger Number on TID Degradation of 16-nm Bulk FinFETs Irradiated to Ultrahigh Doses

This article investigates the fin- and finger-number dependence of the total ionizing dose (TID) degradation in 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs designed with different numbers of fins and fingers are irradiated up to 500 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and then annealed for 24 h at 100 °C. The TID responses of nFinFETs are insensitive to the fin number, as dominated by border and interface trap generation in shallow trench isolation (STI) and/or gate oxide. However, pFinFETs show a visible fin-number dependence with worst tolerance of transistors with the smallest number of fins. The fin number dependence may be related to a larger charge trapping in STI located at the opposite lateral sides of the first and last fins. In addition, both n- and p-FinFETs exhibit an almost TID insensitivity to the finger number. During the design of integrated circuits, the TID tolerance of electronic systems can be enhanced by preferably using transistors with a higher number of fins than fingers.