Device Topology Research Articles

Design and Analysis of Planar Photonic Band Gap Devices

The need for a highly efficient numerical simulation platform for designing photonic band gap (PBG) structures is outlined in the context of various functional device topologies. In this paper we therefore introduce the Method of Auxiliary Sources (MAS) as a semi-analytical, frequency-domain method for computational optics, which has already proven its accuracy and efficiency in various other fields of electrodynamics. The proposed software package provides an easy-to-handle approach to full-wave analysis of two-dimensional (2D) PBG circuits, PBG-based antennas as well as to dense-integrated optics components that contain optical waveguides, scatterers, resonators and other functional elements. Experimental verifications of the numerical results have been conducted along large-scale prototypes in the microwave frequency range for several device topologies.

10-nm Channel Length Pentacene Transistors

Organic thin-film transitors (OTFTs) were fabricated with channel lengths as small as 10 nm and an operating voltage of V/sub DD/=-0.3 V using e-beam lithography. For sub-200-nm channel lengths, scaling L downwards resulted in increased on-current, decreased I/sub on//I/sub off/ ratio, V/sub T/-rolloff, and drain-induced barrier lowering. These trends are correlated with device topology, electrostatics, and thin-film morphology. Nanoscale OTFT are interesting both as a means of studying intrinsic electrical properties of organic materials and as a possible route toward increasing on-current in organic devices. This paper sheds light on many of the issues encountered when shrinking organic devices, providing insight into approaches for optimizing nanoscaled OTFT.

Comparison of SOI Power Device Structures in Power Converters for High-Voltage, Low-Charge Electrostatic Microgenerators

An inertial generator based on a moving-plate capacitor can provide energy for medical sensors from low-frequency (human body) motion. The energy exists as a very small charge (4 nC) at high voltage (300 V). An initial proposal for power processing used a carefully scaled lateral power MOSFET-diode pair, which results in a low, but sufficient, energy yield. It was found that increasing the area of the MOSFET to reduce conduction loss is highly detrimental to the energy yield because of capacitive loading of the generator. This paper examines alternative device topologies which may greatly increase the energy yield for a given system size by increasing both the generation efficiency and the conversion efficiency. An insulated gate bipolar transistors (IGBT) and a MOS-triggered thyristor, both based on previous silicon-on-insulator MOSFET designs, are examined for their switching speed and losses using physics-based finite-element simulation. The scaling criteria to achieve optimum system effectiveness are discussed. The small charge available from the generator results in a brief conduction period which does not allow the devices to reach their steady-state carrier distributions. Nevertheless the IGBT, and especially the MOS-triggered thyristor, switch on faster than the MOSFET, run at higher current densities, and provide improved efficiency. This allows the devices to be reduced in area leading to less capacitive loading on the generator. It also allows a reduction in the value and volume of the circuit inductor without a conduction loss penalty. We describe the device behavior in detail for the various phases of the conversion cycle and illustrate device/circuit tradeoffs graphically. Requirements are outlined for the development of power devices for microgenerators in implanted medical sensors.

Temperature measurement in AlGaN/GaN High-Electron-Mobility Transistors using micro-Raman scattering spectroscopy

High power RF device performance decreases as operation temperature increases (e.g. decreasing electron mobility affects cut-off frequencies and degrades device reliability). Therefore determination of device temperature is a key issue for device topology optimisation. In this work the temperature variation of AlGaN/GaN high-electron-mobility transistors grown either on silicon or sapphire substrate under bias operation was measured by micro Raman scattering spectroscopy. Temperature measurements up to power dissipation of 16 W for 4 mm development devices were carried out and a peak temperature of 650 K was determined. The difference of thermal resistance for similar devices grown on the two different substrates was assessed. The thermal resistances of different device topologies were compared to optimise the component design.

Characterization of a MEMS BioChip for planar patch-clamp recording

We describe a planar MEMS silicon structure to record ion channel currents in biological cells. The conventional method of performing an electrophysiological experiment, `patch-clamping', employs a glass micropipette. The micropipette tip is a source of thermal noise because of its inherent, tapered, conical structure, giving rise to a large pipette resistance. This pipette resistance, when coupled with the biological cell capacitance, limits the available bandwidth of single ion channel recording. In this work, we propose a current transport model to characterize the series resistance and capacitance of a planar pipette fabricated on a silicon BioChip. Our model provides a deeper insight into how currents injected into a micropore are quantitatively partitioned into the individual ion transports, and goes beyond just describing the solute and solvent kinetics inside pores of microscale dimensions. The device topology and fabrication sequence of the planar patch-clamp setup are also discussed. The theoretical predictions by the model are in close agreement with the experimental results.

Temperature measurement by micro-Raman scattering spectroscopy in the active zone of AlGaN/GaN high-electron-mobility transistors

The high power RF device performance decreases as the operation temperature increases (e.g. fall of electron mobility impacting the cut-off frequencies and degradation of device reliability). Therefore the determination of device temperature is a key issue for device topology optimisation. In this work the temperature variation of AlGaN/GaN high-electron-mobility transistors grown either on silicon or sapphire substrates under bias operation was measured by micro Raman scattering spectroscopy. The differences in thermal resistance for similar devices grown on the two different substrates were assessed. The thermal resistances of different device topologies were compared in order to optimise the component design. The temperature measurement across the gate and along the component fingers were made to quantify the thermal gradient of the device. Temperature measurement up to a power dissipation of 16 W for a 4 mm development device was carried out and the peak temperature of 650 K was determined.

The power of using automatic device optimization, based on iterative device simulations, in design of high-performance devices

An automatic optimization tool for semiconductor devices based on iterative device simulations is developed. The tool is used for optimization of different kinds of semiconductor devices using various performance measures. High performance optimization algorithms, both local and global, are used to achieve an efficient design in shortest possible time. In this paper the effects of different optimization algorithms, performance measures, and number of variables in the optimization are studied. Both the computational efficiency and the devices achieved with different performance measures are studied. We give a demonstration of the usefulness of this method in a comparison between different device topologies, which have been optimized for best performance.

A 160-GHz<tex>$f_T$</tex>and 140-GHz<tex>$f_rm MAX$</tex>Submicrometer InP DHBT in MBE Regrown-Emitter Technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.

On the Specific On-Resistance of High-Voltage and Power Devices

This paper establishes for the first time closed-form analytical limits from first-principle on the specific on-resistance, versus breakdown voltage with mobility compensation for all the currently known high-voltage device topologies: vertical DMOS, RESURF, super-junction, and thin-film silicon-on-insulator. The rigorous analytic treatment results in equations purely based on materials constants (relative dielectric constant), well-established fitting parameters (mobility, ionization coefficient), and natural constants (elementary charge, dielectric constant). The results are equally applicable to high-voltage diodes, bipolar devices and junction-FET, but the emphasis is on DMOS structures, which are the device of choice in many applications. Conduction-modulation devices (SCR, TRIAC, IGBT) are not considered here, as the inherent forward diode voltage renders those devices nonlinear at low anode-cathode voltage, making the term "on-resistance (Ron)" meaningless. The theory has been extended by many degrading mechanisms and real-life limitations and excellent agreement with reported results was obtained.

Novel high‐resolution silicon drift detectors

AbstractSilicon drift detectors (SDDs) are used as energy‐dispersive detectors for x‐ray fluorescence analysis in commercial systems. Because of the low capacitance of the readout anode, achieved by the device topology and by the integration of the first FET on the chip, noise contributions are very small, allowing good energy resolution at low shaping times and high count rates. Typical energy resolution is better than 147 eV FWHM at 5.9 keV (Mn Kα), at −10°C. This allows the chips to be cooled with a thermoelectric element, avoiding the use of liquid nitrogen. SDD chips are produced at MPI‐Halbleiterlabor in Munich with different geometries and areas. Recently, a new SDD has been developed which places the anode and the integrated JFET at the margin of the chip where it can easily be shielded from direct irradiation with the use of a collimator. The new layout allows the design of a readout anode with smaller area and therefore reduces the capacitance to values of about 120 fF compared with 200–250 fF with standard SDDs. The result is an improvement in energy resolution down to 128 eV at −15°C. A second effect is the enhancement of the peak‐to‐background values to 6000 homogeneously across the active area of the detector. Copyright © 2004 John Wiley & Sons, Ltd.

Thermal characterisation of AlGaN/GaN HEMTs grown on silicon and sapphire substrates based on pulsed I-V measurements

The high power RF device performance decreases as operation temperature increases ( e.g. fall of electron mobility impacting the cut-off frequencies and degradation of device reliability). Therefore the determination of device temperature is a key issue for device topology optimisation. This work presents the comparison between pulsed I - V at different temperature and DC measurements of AlGaN/GaN HEMTs grown on two different substrates: sapphire and silicon. This technique allows the determination of mean channel temperature and the device thermal resistance. The thermal resistance is a classical way to define the average channel temperature as a function of the dissipated power. In this work the thermal resistance ratio of the HEMT grown on sapphire compared to the one grown on silicon is found to be 1.7 instead of 3 as expected from straightforward thermal conductivity ratio. This lower difference is clearly attributed to the contribution of the GaN buffer layer.

Emission Characteristics of OLEDs on Planar and Non-Planar Substrates

AbstractWe report on light extraction experiments with polyfluorene based organic light emitting diodes (OLEDs). The intensity distribution of emission within the substrate and within air is determined experimentally. For the devices investigated in this study, we find that the external quantum efficiency can be increased by a factor of 1.82, in the case of complete suppression of waveguiding within the substrate. The experimental data is in good agreement with modeling results based on dipole emission within a multilayer system. As a consequence of these findings, we modified the device topology by introducing light extraction structures between glass substrate and indium tin oxide anode. This results in redirection of photon trajectories and thus in a higher probability to extract waveguided radiation. At a luminance of 100 cd/m2, the photometric efficiency for emission in forward direction is enhanced by a factor of 1.45 to 8.9 cd/A.

Laser-induced and heavy ion-induced single-event transient (SET) sensitivity measurements on 139-type comparators

We have measured the single-event transient (SET) response for a number of 139-type comparators with differing topologies. In this paper, we present the results from pulsed laser measurements on a number of different 139-type devices, as well as heavy ion measurements on a new RM139 device from NSC. Devices tested with the laser included the HS-139RH, PM139, LM139 and a more recent version of LM139 from NSC. We discuss the effects of different device topologies on SET sensitivity. Our results agree qualitatively with SPICE model calculations of LM139s by Johnston et al.

Ultralow DC power VCO based on InP-HEMT and heterojunction interband tunnel diode for wireless applications

The monolithic integration of tunneling diodes (TDs) with other semiconductor devices such as high electron-mobility transistors (HEMTs) or HBTs, creates novel quantum functional nonlinear devices and circuits with unique properties: the negative differential resistance and the extremely low dc power consumption. In this paper, we present a family of InP-HEMT-TD-based voltage-controlled oscillators operating in the 4-6-GHz band suitable for wireless applications, along with an effective analytical treatment of the stability issues. Prototypes having different circuit topologies of HEMT-TD devices have been designed and fabricated. The circuits generated an output power in the range of -11 to -18 dBm when operated at a bias current of 1.75 mA at 500 mV. Phase noise characteristics and tuning capability of the circuit configuration have been experimentally determined. The maximum tuning range of 150 MHz and the maximum single sideband-to-carrier ratio of -97 dBc/Hz at 200 kHz have been achieved.

A new high performance phase shifter using Ba/sub x/Sr/sub 1-x/TiO3 thin films

In this paper, a new device topology has been proposed to implement parallel plate capacitors using Ba/sub x/Sr/sub 1-x/TiO/sub 3/ (BST) thin films. The device layout utilizes a single parallel capacitor and minimizes conductor losses in the base electrode. The new design simplifies the monolithic process and overcomes the problems associated with electrode patterning. An X-band 180/spl deg/ phase shifter has been implemented using the new device design. The circuit provided 240/spl deg/ phase shift with an insertion loss of only 3 dB at 10 GHz at room temperature. We have shown a figure of merit 93/spl deg//dB at 6.3 GHz and 87/spl deg//dB at 8.5 GHz. To our knowledge, these are the best figure of merit results reported in the literature for distributed phase shifters implemented using BST films at room temperature.

The semiconductor roadmap for power management in the new millennium

Power management holds the key to over $400 billion annual savings in electrical energy and is relieving critical bottlenecks in the Internet backbone, Internet appliances and portable electronics. The latest analog integrated circuits and power semiconductors are enabling these improvements. This paper focuses on these leading-edge devices, used in conjunction with innovative architectures. The authors examine future trends in silicon-based power transistors and diodes and discuss how the changing requirements of end users are driving new analog ICs, as well as different power management architectures. Trends in architecture for DC-DC power conversion and motion control set the stage for improvements needed and planned in the power management products over the next several years. They examine various technologies for analog ICs and their interface with the digital world. They also compare the pros and cons of different techniques and levels of "power-plus-control integration". The discussion on power MOSFETs (including IGBTs) focuses on performance and technology trends in DC-DC power conversion and motion control. State-of-the-art and future device topologies are presented. The future of diodes is also discussed. DC-DC conversion and motion control is the context. State of the art and future device topologies are presented. Less than 25% of all the world's electricity is efficiently managed. Roadmaps must focus not only on making existing applications more efficient and cost-effective, but also on enabling the new applications that can address the remaining 75%.

Device Innovation and Material Challenges at the Limits of CMOS Technology

▪ Abstract Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

A review of lithium niobate modulators for fiber-optic communications systems

The current status of lithium-niobate external-modulator technology is reviewed with emphasis on design, fabrication, system requirements, performance, and reliability. The technology meets the performance and reliability requirements of current 2.5-, 10-, and 40-Gb/s digital communication systems, as well as CATV analog systems. The current trend in device topology is toward higher data rates and increased levels of integration. In particular, multiple high-speed modulation functions, such as 10-Gb/s return-to-zero pulse generation plus data modulation, have been achieved in a single device.

Analysis of lateral DMOS power devices under ESD stress conditions

The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices.

Silicon two-emitter differential tensotransistor with an accelerating electric field in the base

Results are presented from a study of silicon two-emitter tensotransistors. Tensotransistors are strain-sensitive semiconductor devices with a horizontal structure and an internal differential output. The optimum device topology and its main characteristics are determined. The transfer coefficient of the transistor is close to unity.