Top Oxide Thickness Research Articles

이중게이트 MOSFET의 대칭 및 비대칭 산화막 구조에 대한 문턱전압 분석

본 연구에서는 대칭 및 비대칭 산화막 구조를 가진 이중게이트(double gate; DG) MOSFET의 문턱전압 변화에 대하여 분석하였다. 상하단 동일한 산화막 두께을 갖는 대칭 DGMOSFET와 달리 비대칭 DGMOSFET는 상하단 게이트 산화막 두께를 다르게 제작할 수 있다. 그러므로 비대칭 DGMOSFET에서 상단과 하단게이트 산화막 두께의 크기 변화에 따라 대칭 DGMOSFET와 문턱전압을 비교하여 상하단 게이트 산화막 두께의 최적값에 대하여 고찰하고자 한다. 문턱전압을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 문턱전압 모델을 이용하여 하단게이트 전압, 채널길이 및 채널두께 등에 따라 상하단게이트 산화막 두께가 문턱전압에 미치는 영향을 관찰하였다. 결과적으로 문턱전압은 상하단 게이트 산화막 두께에 따라 크게 변화하였으며 변화하는 경향은 하단게이트 전압, 채널길이 그리고 채널두께에 따라 매우 상이하게 나타나고 있다는 것을 알 수 있었다. This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

비대칭 이중게이트 MOSFET의 상하단 산화막 두께비에 따른 전도중심에 대한 문턱전압 의존성

ABSTRACT This paper has analyzed the change of threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factor to be able to control the current in the subthreshold region increases. The analytical potential distribution is derived from Poisson’s equation to analyze the threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness. The Gaussian distribution function is used as charge distribution. This analytical potential distribution is used to derive off-current and subthreshold swing. By observing the results of threshold voltage and conduction path with parameters of bottom gate voltage, channel length and thickness, projected range and standard projected deviation, the threshold voltage greatly changed for the ratio of top and bottom gate oxide thickness. The threshold voltage changed for the ratio of channel length and thickness, not the absolute values of those, and it increased when conduction path moved toward top gate. The threshold voltage and conduction path changed more greatly for projected range than standard projected deviation.

비대칭 DGMOSFET의 문턱전압이하 스윙에 대한 게이트 산화막 의존성 분석

비대칭 이중게이트(double gate; DG) MOSFET의 문턱전압이하 스윙의 게이트 산화막 두께에 대한 변화를 고찰하였으며 이를 위하여 포아송방정식의 해석학적 전위분포를 구하였다. 특히 포아송방정식을 풀 때 도핑분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였다. 비대칭 DGMOSFET 소자는 대칭적 구조를 갖는 DGMOSFET와 달리 4단자 소자로서 상단과 하단의 게이트 산화막 두께 및 인가전압을 달리 설정할 수 있다. 비대칭 DGMOSFET의 문턱전압이하 스윙을 상 하단 게이트 산화막 두께 변화에 따라 관찰한 결과, 게이트 산화막 두께에 따라 문턱전압이하 스윙은 크게 변화하는 것을 알 수 있었다. 특히 상 하단 게이트 산화막 두께가 증가할 때 문턱전압이하 스윙 값도 증가하였으며 상단 게이트 산화막 두께의 변화가 문턱전압이하 스윙 값에 더욱 큰 영향을 미치고 있다는 것을 알 수 있었다. This paper has presented the change of subthreshold swings for gate oxide thickness of asymmetric double gate(DG) MOSFET, and solved Poisson equation to obtain the analytical solution of potential distribution. The Gaussian function as doping distribution is used to approch experimental results. The symmetric DGMOSFET is three terminal device. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine the bias voltage and oxide thickness for top and bottom gates. As a result to observe the subthreshold swings for the change of top and bottom gate oxide thickness, we know the subthreshold swings are greatly changed for gate oxide thickness. Especially we know the subthreshold swings are increasing with the increase of top and bottom gate oxide thickness, and top gate oxide thickness greatly influences subthreshold swings.

Theory of remote phonon scattering in top-gated single-layer graphene

We extend the theory of interfacial plasmon-phonon scattering to top-gated single-layer graphene. As with bottom-gated graphene, interfacial plasmon-phonon (IPP) modes are formed from the coupling between the graphene plasmon and the surface polar phonon modes in the top and bottom oxides. We study the effect of the top oxide thickness on dynamic screening and electron-IPP coupling. The remote phonon-limited electron mobility ${\ensuremath{\mu}}_{\mathrm{RP}}$ and electron scattering rates in a HfO${}_{2}$-covered, SiO${}_{2}$-supported single-layer graphene are computed at various electron densities $n$ for different dielectric thickness ${t}_{\mathrm{ox}}$. We find that ${\ensuremath{\mu}}_{\mathrm{RP}}$ is much more dependent on ${t}_{\mathrm{ox}}$ at low $n$. They also agree with the experimentally estimated room temperature ${\ensuremath{\mu}}_{\mathrm{RP}}$ from Zou et al. [Phys. Rev. Lett. 105, 126601 (2010)]. The electron density dependent ${\ensuremath{\mu}}_{\mathrm{RP}}$ is predicted to be between 5500 and $24\phantom{\rule{0.16em}{0ex}}200$ cm${}^{2}$V${}^{\ensuremath{-}1}$s${}^{\ensuremath{-}1}$ from $n={10}^{12}$ to ${10}^{13}$ cm${}^{\ensuremath{-}2}$ at 300 K.

Top oxide thickness dependence of remote phonon and charged impurity scattering in top-gated graphene

We have calculated the substrate-limited electron mobility in top-gated, SiO2-supported single-layer graphene from remote-phonon and charged impurity scattering rates. The mobility dependence on gate insulator thickness is explained in terms of the dielectric screening of remote phonons and charged impurities by the high-κ/metal gate. We also find that the effects of high-κ/metal gate screening are reduced at high carrier densities. Of the top gate dielectrics considered (h-BN, HfO2, and Al2O3), h-BN results in a better overall performance and most mobility improvement with a thinner top gate.

Prospect of charge enhancement by increasing top oxide thickness of silicon-on-insulator fin field effect transistors

The variation of electrostatic and transport characteristics of silicon-on-insulator fin field effect transistors (FinFETs) having sub-10 nm fin dimensions is investigated with the variation of top oxide thickness. Capacitance voltage and ballistic transport characteristics of double gate (DG) and triple gate (TG) FinFETs are obtained by self-consistently solving the coupled Schrödinger’s and Poisson’s equations. Performance enhancement can be obtained in terms of both on-state current and inversion capacitance by increasing the top oxide thickness of highly scaled FinFETs. The work suggests limiting values of the device parameter to differentiate the DG and TG variants of FinFET.

Scalability of Atomic-Thin-Body (ATB) Transistors Based on Graphene Nanoribbons

A general solution for the electrostatic potential in an atomic-thin-body field-effect transistor (ATB-FET) geometry is presented. The effective electrostatic scaling length λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> is extracted from the analytical model, which cannot be approximated by the lowest order eigenmode as traditionally done in SOI-MOSFETs. An empirical equation for the scaling length that depends on the geometry parameters is proposed. It is shown that, even for a thick SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> back oxide, λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> can be improved efficiently by a thinner top oxide thickness and, to some extent, with high-k dielectrics. The model is then applied to a self-consistent simulation of graphene nanoribbon (GNR) Schottky-barrier FETs (SB-FETs) at the ballistic limit. In the case of GNR SB-FETs, for a large λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , the scaling is limited by the conventional electrostatic short-channel effects. On the other hand, for a small λ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , the scaling is limited by direct source-to-drain tunneling. A subthreshold swing below 100 mV/dec is still possible with a sub-10-nm gate length in GNR SB-FETs.

Polarization Effect in Laser Processing of Fine Pitch Link Structures for Advanced Memory Designs

Metal fuses for laser redundant links have been widely used for years in laser repair application to enhance yield. Shrinking design rules in IC fabrication have necessitated decreased fuse pitches in the redundancy circuitry. Current infrared lasers are facing the 2 mum pitch barrier due to the diffraction limited spot size and depth of focus capabilities. In this paper, we present experimental results showing how we have achieved successful laser cut processes of future metal fuse structures down to 1.0 mum pitch using a combination of the small spot of short wavelength laser and the polarization effect to tightly pitched neighbor structures. Inline polarization with link length minimizes the adjacent link damages and thus improves the energy process window for robust cutting. Electrical measurement data of metal link structures with various pitches, metal width and top passivation thicknesses shows the importance of controlling of top oxide thickness on the fine pitch structure. This enabling technology provides a viable production solution for laser fuse processing down to 45-nm node technology and below.

Effect of Rapid Thermal Annealing in N2 and Stacked Layer on SiO2–Al2O3–SiO2 Characteristics for Interpoly Silicon Dielectrics

In this paper, we present a thorough investigation of the physical and electrical characteristics of a SiO2/Al2O3/SiO2 (OAO) stack film. The crystallization temperature of an aluminum oxide (Al2O3) material of 9.2 nm thickness is about 925 °C, and leakage current is determined by trap-assisted tunneling (TAT) in the low E-field region owing to grain boundary formation. Nevertheless, crystalline Al2O3 can increase dielectric constant, lower band gap, and cause offset of conduction band (ΔEC); thus, a lower leakage is obtained in high E-field region. Comparing various films with the scheme of SiO2/Al2O3/SiO2 and presented at various post deposition annealing (PDA) temperatures, it is found that the top oxide thickness and crystallization temperature of the Al2O3 material play key factors for high electric strength and electron trapping. Our experiment demonstrated that a specific SiO2/Al2O3/SiO2 stack film incorporated with an appropriate thermal budget for Al2O3 annealing can be utilized for future NAND flash memory cells.

Control of Subthreshold Characteristics of Narrow-Channel Silicon-on-Insulator n-Type Metal–Oxide–Semiconductor Transistor with Additional Side Gate Electrodes

A silicon-on-insulator (SOI) n-type metal–oxide–semiconductor (MOS) transistor with additional side gate electrodes is fabricated and its subthreshold characteristics are discussed. Since its device structure provides independent biasing to gates, flexible device-characteristic control for the respective device is expected. The key fabrication process is the formation of transistor gates. Additional side gate electrodes are formed by reactive ion etching (RIE) with a SiO2-covered top gate as an etching mask. Subthreshold characteristics are improved by negative side-gate biasing. In addition, the side-gate voltage VSG required to decrease off-leakage current by one decade is around 100 mV. Since the sidewall oxide thickness is chosen to be 5 nm, which is the same as the top-oxide thickness, rather sensitive subthreshold-characteristic control compared with that of biasing through a thick buried-oxide layer is achieved in response to performance requirement. In the viewpoint of stand-by-power suppression, these provide a certain controllability to a circuit operation.

Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Device design using body-tied fin field effect transistor (bulk FinFET) was considered for the application to 50 nm DRAM technology. We concentrated on the device characteristics such as threshold voltage (Vth), off-state leakage current (Ioff), subthreshold swing (S.S), and drain induced barrier lowering (DIBL) by controlling lightly doped drain (LDD) profile of the bulk FinFET. Bulk FinFETs with 0 to 3 nm non-overlap between source/drain (S/D) to gate electrode show lower Ioff, S.S, and DIBL than those with an overlap while maintaining reasonable threshold voltage. We also compared characteristics of the triple gate bulk FinFET with those of the double gate bulk FinFET. Finally, electrical characteristics with LDD doping profile, S/D to gate overlap length, top gate oxide thickness, body doping concentration, fin top doping concentration, and doping profile from the edge to the center of the fin body are also compared.

Metrology issues in thin ONO stacks measurements by spectroscopic ellipsometry and X-ray reflectivity

We performed X-ray reflectivity (XRR) and spectroscopic ellipsometry (SE) analysis of several ONO stacks with different deposition conditions. TEM was also used as reference technique. In the energy range from 1.5 to 6.5 eV, SE analysis shows a correlation between bottom and top oxide thickness. The small electron density difference between Si and SiO 2 makes the SiO 2/Si interface determination difficult to estimate by XRR. By etch profiling we observed a relatively large extension of the oxide/nitride interfaces. Comparing the results of both techniques, we have observed major differences in thickness estimation. Most of these differences can be attributed to an estimation and weighting of the interfaces among the different techniques are considered in this paper.

Etching behavior of Si-containing polymers as resist materials for bilayer lithography: The case of poly-dimethyl siloxane

This work is focused on the plasma development of siloxanes investigated as model Si-containing photoresist components that show a promise for bilayer lithography at 157 nm and other Next Generation Lithography technologies. In such lithography, the image is developed in the top photosensitive polymer and transferred to the (usually thick) organic underlayer by means of O2-based plasma etching. In this work particularly, the issue of line edge roughness (LER) induced by transfer etching and its reduction by means of plasma processing optimization is addressed. The experimental results reveal that low values of line-edge roughness are obtained in a high-density plasma reactor, if an F- but not O-containing etching first step is used in appropriate plasma conditions. The effect of different etching chemistries and processing conditions on imaging layer roughness formation is demonstrated with the aid of scanning electron microscopy images and image analysis for quantifying LER, and atomic force microscopy (AFM) for measuring surface roughness. X-ray photoelectron spectroscopy analysis of etched PDMS is used to show the evolution of the chemical modification of the PDMS layer, to measure the top oxide thickness, and to correlate both to processing conditions. In situ interferometry and ellipsometry are used to determine the etch resistance of the imaging PDMS layer and the selectivity of the transfer etching process. It is demonstrated that optimum LER correlates well with plasma processing conditions that ensure a nonselective first etching step prior to a highly selective main etching.

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications.

Conduction and Charge‐Trapping Characteristics of MOS Capacitors with Oxidized Nitride Films of Different Nitride Thicknesses under Positive Stress Bias

Metal oxide semiconductor capacitors with oxidized thick and thin nitride films of two different nitride thicknesses were used to study the conduction and charge‐trapping behavior under positive stress bias to the upper electrode. Although the top oxide thickness of the two groups of oxidized nitride films is the same, the charge‐trapping characteristics are different. It was found that due to the positive stress to the upper electrode of oxidized thick nitride, the gate voltage is shifted to the negative direction, whereas in oxidized thin nitride, it is shifted to the positive direction, just like the nitride films. It was also observed that in nitride films, irrespective of nitride thickness, due to the positive stress bias, the gate voltage is shifted to the positive direction. From the experimental results of oxidized thick and thin nitride, it can be inferred that in oxidized thick nitride, due to electron injection from the lower electrode, holes are generated in the nitride film and are trapped near the interface. As a result of trapped holes near the interface of the top oxide and nitride, as well as a shallow electron trap centered below the conduction band of the nitride, a large increase in current is observed in oxidized thick nitride. On the other hand, in oxidized thin nitride films for the same positive stress bias, only a few holes are generated in the nitride film because most of the injected electrons from the lower electrode tunnel through the nitride and are trapped in the top oxide. Also shallow trap centers are generated below the conduction band of the thin nitride films. As a result of fewer trapped holes in the interface, the increase of current in oxidized thin nitride is less compared with those of oxidized thick nitride.

A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10/sup 7/ erase/write cycles

A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor (MONOS) structure whose top oxide is fabricated by chemical vapor deposition (CVD) on the nitride is proposed. This CVD oxide is densified by pyrogenic annealing and has stoichiometric SiO/sub 2/ characteristics. Its potential barrier, which prevents stored charges from decaying through the top oxide to the gate, thus becomes sharper than that of the thermally grown top oxide used in the conventional MONOS structure. For comparison between the proposed MONOS, conventional MONOS, and MNOS structures, three devices were fabricated on the same process line. The 16.7-nm nitride thickness in combination with a top oxide thickness of 4.0 nm results in a gate capacitance equivalent to that of the conventional NMOS structure with a 23.5-nm nitride thickness. Moreover, an asymmetric erase/write programming voltage has been adapted to the MONOS device operation by considering both erased-state degradation and written-state retention. At 85 degrees C, the proposed MONOS device has 10/sup 7/-cycle endurance with 10-year data retention. >

ONO inter-poly dielectric scaling for nonvolatile memory applications

The ONO (oxide/nitride/oxide) inter-poly dielectric thickness scaling effect on electric-field-leakage-current characteristics and charge retention characteristics in nonvolatile memories are investigated. Surface top-oxide thickness strongly affects the charge leakage and retention characteristics. Thicker than 3 nm top oxide can block hole injunction from the anode. Thick top oxide can reduce leakage current in both high and low electric field regions. Moreover, it can improve charge retention characteristics in nonvolatile memory cells. Therefore, a certain amount of top oxide is required to preserve good charge retention characteristics. SiN thickness scaling leads to an improvement in charge retention characteristics. Bottom oxide has an important role in suppressing electron leakage in a low electric field region. A degraded quality thin bottom oxide leads to charge retention capability degradation. Therefore, bottom-oxide quality and thickness control is an important subject for ONO thickness scaling. >

Reliability of 10 nm Stacked Insulator on Polycrystalline Silicon in Planar and Trench Capacitors

The reliability of three types of stacked insulating films (ONO, ON, NO) with thicknesses of 10 nm and below deposited on highly doped polysilicon are compared. It is shown that the doping process of the underlaying polysilicon plays an important role in the dielectric breakdown behavior. Evaluation of I‐E characteristics from voltage ramp measurements demonstrates the influence of top and bottom oxide thickness. Under NO double layers generally a native oxide is found. This leads to similar reliability results as found for triple layers. Real double layers (ON) without any potential barrier at the top electrode show significantly shorter lifetimes at positive gate voltage. Hence the native oxide between bottom electrode and nitride is not negligible. Extrapolations of the data measured by the constant voltage method on planar and trench capacitors indicate that the investigated ultrathin multilayer films on polysilicon show promise as dielectrics in storage capacitors of future DRAMs.

Conduction properties of silicon dioxide in oxide-nitride-oxide structures

Conduction properties of silicon dioxide have been investigated in polysilicon-oxidized silicon nitride (top-oxide)-silicon nitride-silicon dioxide (bottom-oxide)-silicon structures with various nitride and top-oxide thicknesses. Oxidized silicon nitride was found to exhibit electron tunneling limited (Fowler-Nordheim-type) conduction. Electron Fowler-Nordheim conduction in the relatively thick (⋍ 100 Å) bottom-oxide was verified down to very low electric fields (⋍ 5 MV/cm).

Traps created at the interface between the nitride and the oxide on the nitride by thermal oxidation

Traps introduced by thermal oxidation of a thin nitride film have been investigated using metal-oxide (top-oxide)-nitride-oxide-semiconductor memory diodes. Memory properties as a function of the initial nitride thickness before thermal oxidation and the top-oxide thickness have revealed that the newly created traps are situated mostly at the top-oxide-nitride interface. The density of the traps is estimated to be (1.6±0.2)×1013/cm2 independent of the initial nitride thickness and the top-oxide thickness.